mirror of
https://github.com/Wind4/vlmcsd.git
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vlmcsd-svn1065-2016-10-12-Hotbird64
This commit is contained in:
Wind4
@ -0,0 +1,20 @@
|
||||
#ifndef _ASM_X86_A_OUT_H
|
||||
#define _ASM_X86_A_OUT_H
|
||||
|
||||
struct exec
|
||||
{
|
||||
unsigned int a_info; /* Use macros N_MAGIC, etc for access */
|
||||
unsigned a_text; /* length of text, in bytes */
|
||||
unsigned a_data; /* length of data, in bytes */
|
||||
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
|
||||
unsigned a_syms; /* length of symbol table data in file, in bytes */
|
||||
unsigned a_entry; /* start address */
|
||||
unsigned a_trsize; /* length of relocation info for text, in bytes */
|
||||
unsigned a_drsize; /* length of relocation info for data, in bytes */
|
||||
};
|
||||
|
||||
#define N_TRSIZE(a) ((a).a_trsize)
|
||||
#define N_DRSIZE(a) ((a).a_drsize)
|
||||
#define N_SYMSIZE(a) ((a).a_syms)
|
||||
|
||||
#endif /* _ASM_X86_A_OUT_H */
|
||||
@ -0,0 +1,19 @@
|
||||
#ifndef _ASM_X86_AUXVEC_H
|
||||
#define _ASM_X86_AUXVEC_H
|
||||
/*
|
||||
* Architecture-neutral AT_ values in 0-17, leave some room
|
||||
* for more of them, start the x86-specific ones at 32.
|
||||
*/
|
||||
#ifdef __i386__
|
||||
#define AT_SYSINFO 32
|
||||
#endif
|
||||
#define AT_SYSINFO_EHDR 33
|
||||
|
||||
/* entries in ARCH_DLINFO: */
|
||||
#if defined(CONFIG_IA32_EMULATION) || !defined(CONFIG_X86_64)
|
||||
# define AT_VECTOR_SIZE_ARCH 2
|
||||
#else /* else it's non-compat x86-64 */
|
||||
# define AT_VECTOR_SIZE_ARCH 1
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_X86_AUXVEC_H */
|
||||
@ -0,0 +1,13 @@
|
||||
#ifndef __ASM_X86_BITSPERLONG_H
|
||||
#define __ASM_X86_BITSPERLONG_H
|
||||
|
||||
#if defined(__x86_64__) && !defined(__ILP32__)
|
||||
# define __BITS_PER_LONG 64
|
||||
#else
|
||||
# define __BITS_PER_LONG 32
|
||||
#endif
|
||||
|
||||
#include <asm-generic/bitsperlong.h>
|
||||
|
||||
#endif /* __ASM_X86_BITSPERLONG_H */
|
||||
|
||||
@ -0,0 +1,10 @@
|
||||
#ifndef _ASM_X86_BOOT_H
|
||||
#define _ASM_X86_BOOT_H
|
||||
|
||||
/* Internal svga startup constants */
|
||||
#define NORMAL_VGA 0xffff /* 80x25 mode */
|
||||
#define EXTENDED_VGA 0xfffe /* 80x50 mode */
|
||||
#define ASK_VGA 0xfffd /* ask for it at bootup */
|
||||
|
||||
|
||||
#endif /* _ASM_X86_BOOT_H */
|
||||
@ -0,0 +1,172 @@
|
||||
#ifndef _ASM_X86_BOOTPARAM_H
|
||||
#define _ASM_X86_BOOTPARAM_H
|
||||
|
||||
/* setup_data types */
|
||||
#define SETUP_NONE 0
|
||||
#define SETUP_E820_EXT 1
|
||||
#define SETUP_DTB 2
|
||||
#define SETUP_PCI 3
|
||||
#define SETUP_EFI 4
|
||||
|
||||
/* ram_size flags */
|
||||
#define RAMDISK_IMAGE_START_MASK 0x07FF
|
||||
#define RAMDISK_PROMPT_FLAG 0x8000
|
||||
#define RAMDISK_LOAD_FLAG 0x4000
|
||||
|
||||
/* loadflags */
|
||||
#define LOADED_HIGH (1<<0)
|
||||
#define KASLR_FLAG (1<<1)
|
||||
#define QUIET_FLAG (1<<5)
|
||||
#define KEEP_SEGMENTS (1<<6)
|
||||
#define CAN_USE_HEAP (1<<7)
|
||||
|
||||
/* xloadflags */
|
||||
#define XLF_KERNEL_64 (1<<0)
|
||||
#define XLF_CAN_BE_LOADED_ABOVE_4G (1<<1)
|
||||
#define XLF_EFI_HANDOVER_32 (1<<2)
|
||||
#define XLF_EFI_HANDOVER_64 (1<<3)
|
||||
#define XLF_EFI_KEXEC (1<<4)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/screen_info.h>
|
||||
#include <linux/apm_bios.h>
|
||||
#include <linux/edd.h>
|
||||
#include <asm/e820.h>
|
||||
#include <asm/ist.h>
|
||||
#include <video/edid.h>
|
||||
|
||||
/* extensible setup data list node */
|
||||
struct setup_data {
|
||||
__u64 next;
|
||||
__u32 type;
|
||||
__u32 len;
|
||||
__u8 data[0];
|
||||
};
|
||||
|
||||
struct setup_header {
|
||||
__u8 setup_sects;
|
||||
__u16 root_flags;
|
||||
__u32 syssize;
|
||||
__u16 ram_size;
|
||||
__u16 vid_mode;
|
||||
__u16 root_dev;
|
||||
__u16 boot_flag;
|
||||
__u16 jump;
|
||||
__u32 header;
|
||||
__u16 version;
|
||||
__u32 realmode_swtch;
|
||||
__u16 start_sys;
|
||||
__u16 kernel_version;
|
||||
__u8 type_of_loader;
|
||||
__u8 loadflags;
|
||||
__u16 setup_move_size;
|
||||
__u32 code32_start;
|
||||
__u32 ramdisk_image;
|
||||
__u32 ramdisk_size;
|
||||
__u32 bootsect_kludge;
|
||||
__u16 heap_end_ptr;
|
||||
__u8 ext_loader_ver;
|
||||
__u8 ext_loader_type;
|
||||
__u32 cmd_line_ptr;
|
||||
__u32 initrd_addr_max;
|
||||
__u32 kernel_alignment;
|
||||
__u8 relocatable_kernel;
|
||||
__u8 min_alignment;
|
||||
__u16 xloadflags;
|
||||
__u32 cmdline_size;
|
||||
__u32 hardware_subarch;
|
||||
__u64 hardware_subarch_data;
|
||||
__u32 payload_offset;
|
||||
__u32 payload_length;
|
||||
__u64 setup_data;
|
||||
__u64 pref_address;
|
||||
__u32 init_size;
|
||||
__u32 handover_offset;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct sys_desc_table {
|
||||
__u16 length;
|
||||
__u8 table[14];
|
||||
};
|
||||
|
||||
/* Gleaned from OFW's set-parameters in cpu/x86/pc/linux.fth */
|
||||
struct olpc_ofw_header {
|
||||
__u32 ofw_magic; /* OFW signature */
|
||||
__u32 ofw_version;
|
||||
__u32 cif_handler; /* callback into OFW */
|
||||
__u32 irq_desc_table;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct efi_info {
|
||||
__u32 efi_loader_signature;
|
||||
__u32 efi_systab;
|
||||
__u32 efi_memdesc_size;
|
||||
__u32 efi_memdesc_version;
|
||||
__u32 efi_memmap;
|
||||
__u32 efi_memmap_size;
|
||||
__u32 efi_systab_hi;
|
||||
__u32 efi_memmap_hi;
|
||||
};
|
||||
|
||||
/* The so-called "zeropage" */
|
||||
struct boot_params {
|
||||
struct screen_info screen_info; /* 0x000 */
|
||||
struct apm_bios_info apm_bios_info; /* 0x040 */
|
||||
__u8 _pad2[4]; /* 0x054 */
|
||||
__u64 tboot_addr; /* 0x058 */
|
||||
struct ist_info ist_info; /* 0x060 */
|
||||
__u8 _pad3[16]; /* 0x070 */
|
||||
__u8 hd0_info[16]; /* obsolete! */ /* 0x080 */
|
||||
__u8 hd1_info[16]; /* obsolete! */ /* 0x090 */
|
||||
struct sys_desc_table sys_desc_table; /* obsolete! */ /* 0x0a0 */
|
||||
struct olpc_ofw_header olpc_ofw_header; /* 0x0b0 */
|
||||
__u32 ext_ramdisk_image; /* 0x0c0 */
|
||||
__u32 ext_ramdisk_size; /* 0x0c4 */
|
||||
__u32 ext_cmd_line_ptr; /* 0x0c8 */
|
||||
__u8 _pad4[116]; /* 0x0cc */
|
||||
struct edid_info edid_info; /* 0x140 */
|
||||
struct efi_info efi_info; /* 0x1c0 */
|
||||
__u32 alt_mem_k; /* 0x1e0 */
|
||||
__u32 scratch; /* Scratch field! */ /* 0x1e4 */
|
||||
__u8 e820_entries; /* 0x1e8 */
|
||||
__u8 eddbuf_entries; /* 0x1e9 */
|
||||
__u8 edd_mbr_sig_buf_entries; /* 0x1ea */
|
||||
__u8 kbd_status; /* 0x1eb */
|
||||
__u8 secure_boot; /* 0x1ec */
|
||||
__u8 _pad5[2]; /* 0x1ed */
|
||||
/*
|
||||
* The sentinel is set to a nonzero value (0xff) in header.S.
|
||||
*
|
||||
* A bootloader is supposed to only take setup_header and put
|
||||
* it into a clean boot_params buffer. If it turns out that
|
||||
* it is clumsy or too generous with the buffer, it most
|
||||
* probably will pick up the sentinel variable too. The fact
|
||||
* that this variable then is still 0xff will let kernel
|
||||
* know that some variables in boot_params are invalid and
|
||||
* kernel should zero out certain portions of boot_params.
|
||||
*/
|
||||
__u8 sentinel; /* 0x1ef */
|
||||
__u8 _pad6[1]; /* 0x1f0 */
|
||||
struct setup_header hdr; /* setup header */ /* 0x1f1 */
|
||||
__u8 _pad7[0x290-0x1f1-sizeof(struct setup_header)];
|
||||
__u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX]; /* 0x290 */
|
||||
struct e820entry e820_map[E820MAX]; /* 0x2d0 */
|
||||
__u8 _pad8[48]; /* 0xcd0 */
|
||||
struct edd_info eddbuf[EDDMAXNR]; /* 0xd00 */
|
||||
__u8 _pad9[276]; /* 0xeec */
|
||||
} __attribute__((packed));
|
||||
|
||||
enum {
|
||||
X86_SUBARCH_PC = 0,
|
||||
X86_SUBARCH_LGUEST,
|
||||
X86_SUBARCH_XEN,
|
||||
X86_SUBARCH_INTEL_MID,
|
||||
X86_SUBARCH_CE4100,
|
||||
X86_NR_SUBARCHS,
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_X86_BOOTPARAM_H */
|
||||
@ -0,0 +1,6 @@
|
||||
#ifndef _ASM_X86_BYTEORDER_H
|
||||
#define _ASM_X86_BYTEORDER_H
|
||||
|
||||
#include <linux/byteorder/little_endian.h>
|
||||
|
||||
#endif /* _ASM_X86_BYTEORDER_H */
|
||||
@ -0,0 +1,80 @@
|
||||
#ifndef _ASM_X86_DEBUGREG_H
|
||||
#define _ASM_X86_DEBUGREG_H
|
||||
|
||||
|
||||
/* Indicate the register numbers for a number of the specific
|
||||
debug registers. Registers 0-3 contain the addresses we wish to trap on */
|
||||
#define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */
|
||||
#define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */
|
||||
|
||||
#define DR_STATUS 6 /* u_debugreg[DR_STATUS] */
|
||||
#define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */
|
||||
|
||||
/* Define a few things for the status register. We can use this to determine
|
||||
which debugging register was responsible for the trap. The other bits
|
||||
are either reserved or not of interest to us. */
|
||||
|
||||
/* Define reserved bits in DR6 which are always set to 1 */
|
||||
#define DR6_RESERVED (0xFFFF0FF0)
|
||||
|
||||
#define DR_TRAP0 (0x1) /* db0 */
|
||||
#define DR_TRAP1 (0x2) /* db1 */
|
||||
#define DR_TRAP2 (0x4) /* db2 */
|
||||
#define DR_TRAP3 (0x8) /* db3 */
|
||||
#define DR_TRAP_BITS (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)
|
||||
|
||||
#define DR_STEP (0x4000) /* single-step */
|
||||
#define DR_SWITCH (0x8000) /* task switch */
|
||||
|
||||
/* Now define a bunch of things for manipulating the control register.
|
||||
The top two bytes of the control register consist of 4 fields of 4
|
||||
bits - each field corresponds to one of the four debug registers,
|
||||
and indicates what types of access we trap on, and how large the data
|
||||
field is that we are looking at */
|
||||
|
||||
#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
|
||||
#define DR_CONTROL_SIZE 4 /* 4 control bits per register */
|
||||
|
||||
#define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */
|
||||
#define DR_RW_WRITE (0x1)
|
||||
#define DR_RW_READ (0x3)
|
||||
|
||||
#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
|
||||
#define DR_LEN_2 (0x4)
|
||||
#define DR_LEN_4 (0xC)
|
||||
#define DR_LEN_8 (0x8)
|
||||
|
||||
/* The low byte to the control register determine which registers are
|
||||
enabled. There are 4 fields of two bits. One bit is "local", meaning
|
||||
that the processor will reset the bit after a task switch and the other
|
||||
is global meaning that we have to explicitly reset the bit. With linux,
|
||||
you can use either one, since we explicitly zero the register when we enter
|
||||
kernel mode. */
|
||||
|
||||
#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */
|
||||
#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
|
||||
#define DR_LOCAL_ENABLE (0x1) /* Local enable for reg 0 */
|
||||
#define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */
|
||||
#define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
|
||||
|
||||
#define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
|
||||
#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
|
||||
|
||||
/* The second byte to the control register has a few special things.
|
||||
We can slow the instruction pipeline for instructions coming via the
|
||||
gdt or the ldt if we want to. I am not sure why this is an advantage */
|
||||
|
||||
#ifdef __i386__
|
||||
#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
|
||||
#else
|
||||
#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
|
||||
#endif
|
||||
|
||||
#define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */
|
||||
#define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
|
||||
|
||||
/*
|
||||
* HW breakpoint additions
|
||||
*/
|
||||
|
||||
#endif /* _ASM_X86_DEBUGREG_H */
|
||||
@ -0,0 +1,79 @@
|
||||
#ifndef _ASM_X86_E820_H
|
||||
#define _ASM_X86_E820_H
|
||||
#define E820MAP 0x2d0 /* our map */
|
||||
#define E820MAX 128 /* number of entries in E820MAP */
|
||||
|
||||
/*
|
||||
* Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the
|
||||
* constrained space in the zeropage. If we have more nodes than
|
||||
* that, and if we've booted off EFI firmware, then the EFI tables
|
||||
* passed us from the EFI firmware can list more nodes. Size our
|
||||
* internal memory map tables to have room for these additional
|
||||
* nodes, based on up to three entries per node for which the
|
||||
* kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT),
|
||||
* plus E820MAX, allowing space for the possible duplicate E820
|
||||
* entries that might need room in the same arrays, prior to the
|
||||
* call to sanitize_e820_map() to remove duplicates. The allowance
|
||||
* of three memory map entries per node is "enough" entries for
|
||||
* the initial hardware platform motivating this mechanism to make
|
||||
* use of additional EFI map entries. Future platforms may want
|
||||
* to allow more than three entries per node or otherwise refine
|
||||
* this size.
|
||||
*/
|
||||
|
||||
#define E820_X_MAX E820MAX
|
||||
|
||||
#define E820NR 0x1e8 /* # entries in E820MAP */
|
||||
|
||||
#define E820_RAM 1
|
||||
#define E820_RESERVED 2
|
||||
#define E820_ACPI 3
|
||||
#define E820_NVS 4
|
||||
#define E820_UNUSABLE 5
|
||||
#define E820_PMEM 7
|
||||
|
||||
/*
|
||||
* This is a non-standardized way to represent ADR or NVDIMM regions that
|
||||
* persist over a reboot. The kernel will ignore their special capabilities
|
||||
* unless the CONFIG_X86_PMEM_LEGACY option is set.
|
||||
*
|
||||
* ( Note that older platforms also used 6 for the same type of memory,
|
||||
* but newer versions switched to 12 as 6 was assigned differently. Some
|
||||
* time they will learn... )
|
||||
*/
|
||||
#define E820_PRAM 12
|
||||
|
||||
/*
|
||||
* reserved RAM used by kernel itself
|
||||
* if CONFIG_INTEL_TXT is enabled, memory of this type will be
|
||||
* included in the S3 integrity calculation and so should not include
|
||||
* any memory that BIOS might alter over the S3 transition
|
||||
*/
|
||||
#define E820_RESERVED_KERN 128
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/types.h>
|
||||
struct e820entry {
|
||||
__u64 addr; /* start of memory segment */
|
||||
__u64 size; /* size of memory segment */
|
||||
__u32 type; /* type of memory segment */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct e820map {
|
||||
__u32 nr_map;
|
||||
struct e820entry map[E820_X_MAX];
|
||||
};
|
||||
|
||||
#define ISA_START_ADDRESS 0xa0000
|
||||
#define ISA_END_ADDRESS 0x100000
|
||||
|
||||
#define BIOS_BEGIN 0x000a0000
|
||||
#define BIOS_END 0x00100000
|
||||
|
||||
#define BIOS_ROM_BASE 0xffe00000
|
||||
#define BIOS_ROM_END 0xffffffff
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
||||
#endif /* _ASM_X86_E820_H */
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/errno.h>
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/fcntl.h>
|
||||
@ -0,0 +1 @@
|
||||
/* */
|
||||
@ -0,0 +1,366 @@
|
||||
#ifndef _ASM_X86_HYPERV_H
|
||||
#define _ASM_X86_HYPERV_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
* The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
|
||||
* is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
|
||||
*/
|
||||
#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
|
||||
#define HYPERV_CPUID_INTERFACE 0x40000001
|
||||
#define HYPERV_CPUID_VERSION 0x40000002
|
||||
#define HYPERV_CPUID_FEATURES 0x40000003
|
||||
#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
|
||||
#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
|
||||
|
||||
#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
|
||||
#define HYPERV_CPUID_MIN 0x40000005
|
||||
#define HYPERV_CPUID_MAX 0x4000ffff
|
||||
|
||||
/*
|
||||
* Feature identification. EAX indicates which features are available
|
||||
* to the partition based upon the current partition privileges.
|
||||
*/
|
||||
|
||||
/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
|
||||
#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0)
|
||||
/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
|
||||
#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
|
||||
/* Partition reference TSC MSR is available */
|
||||
#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9)
|
||||
|
||||
/* A partition's reference time stamp counter (TSC) page */
|
||||
#define HV_X64_MSR_REFERENCE_TSC 0x40000021
|
||||
|
||||
/*
|
||||
* There is a single feature flag that signifies the presence of the MSR
|
||||
* that can be used to retrieve both the local APIC Timer frequency as
|
||||
* well as the TSC frequency.
|
||||
*/
|
||||
|
||||
/* Local APIC timer frequency MSR (HV_X64_MSR_APIC_FREQUENCY) is available */
|
||||
#define HV_X64_MSR_APIC_FREQUENCY_AVAILABLE (1 << 11)
|
||||
|
||||
/* TSC frequency MSR (HV_X64_MSR_TSC_FREQUENCY) is available */
|
||||
#define HV_X64_MSR_TSC_FREQUENCY_AVAILABLE (1 << 11)
|
||||
|
||||
/*
|
||||
* Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
|
||||
* and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
|
||||
*/
|
||||
#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2)
|
||||
/*
|
||||
* Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
|
||||
* HV_X64_MSR_STIMER3_COUNT) available
|
||||
*/
|
||||
#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3)
|
||||
/*
|
||||
* APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
|
||||
* are available
|
||||
*/
|
||||
#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4)
|
||||
/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
|
||||
#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5)
|
||||
/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
|
||||
#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6)
|
||||
/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
|
||||
#define HV_X64_MSR_RESET_AVAILABLE (1 << 7)
|
||||
/*
|
||||
* Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
|
||||
* HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
|
||||
* HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
|
||||
*/
|
||||
#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8)
|
||||
|
||||
/*
|
||||
* Feature identification: EBX indicates which flags were specified at
|
||||
* partition creation. The format is the same as the partition creation
|
||||
* flag structure defined in section Partition Creation Flags.
|
||||
*/
|
||||
#define HV_X64_CREATE_PARTITIONS (1 << 0)
|
||||
#define HV_X64_ACCESS_PARTITION_ID (1 << 1)
|
||||
#define HV_X64_ACCESS_MEMORY_POOL (1 << 2)
|
||||
#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3)
|
||||
#define HV_X64_POST_MESSAGES (1 << 4)
|
||||
#define HV_X64_SIGNAL_EVENTS (1 << 5)
|
||||
#define HV_X64_CREATE_PORT (1 << 6)
|
||||
#define HV_X64_CONNECT_PORT (1 << 7)
|
||||
#define HV_X64_ACCESS_STATS (1 << 8)
|
||||
#define HV_X64_DEBUGGING (1 << 11)
|
||||
#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12)
|
||||
#define HV_X64_CONFIGURE_PROFILER (1 << 13)
|
||||
|
||||
/*
|
||||
* Feature identification. EDX indicates which miscellaneous features
|
||||
* are available to the partition.
|
||||
*/
|
||||
/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
|
||||
#define HV_X64_MWAIT_AVAILABLE (1 << 0)
|
||||
/* Guest debugging support is available */
|
||||
#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1)
|
||||
/* Performance Monitor support is available*/
|
||||
#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2)
|
||||
/* Support for physical CPU dynamic partitioning events is available*/
|
||||
#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3)
|
||||
/*
|
||||
* Support for passing hypercall input parameter block via XMM
|
||||
* registers is available
|
||||
*/
|
||||
#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4)
|
||||
/* Support for a virtual guest idle state is available */
|
||||
#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5)
|
||||
/* Guest crash data handler available */
|
||||
#define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
|
||||
|
||||
/*
|
||||
* Implementation recommendations. Indicates which behaviors the hypervisor
|
||||
* recommends the OS implement for optimal performance.
|
||||
*/
|
||||
/*
|
||||
* Recommend using hypercall for address space switches rather
|
||||
* than MOV to CR3 instruction
|
||||
*/
|
||||
#define HV_X64_MWAIT_RECOMMENDED (1 << 0)
|
||||
/* Recommend using hypercall for local TLB flushes rather
|
||||
* than INVLPG or MOV to CR3 instructions */
|
||||
#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1)
|
||||
/*
|
||||
* Recommend using hypercall for remote TLB flushes rather
|
||||
* than inter-processor interrupts
|
||||
*/
|
||||
#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2)
|
||||
/*
|
||||
* Recommend using MSRs for accessing APIC registers
|
||||
* EOI, ICR and TPR rather than their memory-mapped counterparts
|
||||
*/
|
||||
#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3)
|
||||
/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
|
||||
#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4)
|
||||
/*
|
||||
* Recommend using relaxed timing for this partition. If used,
|
||||
* the VM should disable any watchdog timeouts that rely on the
|
||||
* timely delivery of external interrupts
|
||||
*/
|
||||
#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5)
|
||||
|
||||
/* MSR used to identify the guest OS. */
|
||||
#define HV_X64_MSR_GUEST_OS_ID 0x40000000
|
||||
|
||||
/* MSR used to setup pages used to communicate with the hypervisor. */
|
||||
#define HV_X64_MSR_HYPERCALL 0x40000001
|
||||
|
||||
/* MSR used to provide vcpu index */
|
||||
#define HV_X64_MSR_VP_INDEX 0x40000002
|
||||
|
||||
/* MSR used to reset the guest OS. */
|
||||
#define HV_X64_MSR_RESET 0x40000003
|
||||
|
||||
/* MSR used to provide vcpu runtime in 100ns units */
|
||||
#define HV_X64_MSR_VP_RUNTIME 0x40000010
|
||||
|
||||
/* MSR used to read the per-partition time reference counter */
|
||||
#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
|
||||
|
||||
/* MSR used to retrieve the TSC frequency */
|
||||
#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
|
||||
|
||||
/* MSR used to retrieve the local APIC timer frequency */
|
||||
#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
|
||||
|
||||
/* Define the virtual APIC registers */
|
||||
#define HV_X64_MSR_EOI 0x40000070
|
||||
#define HV_X64_MSR_ICR 0x40000071
|
||||
#define HV_X64_MSR_TPR 0x40000072
|
||||
#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
|
||||
|
||||
/* Define synthetic interrupt controller model specific registers. */
|
||||
#define HV_X64_MSR_SCONTROL 0x40000080
|
||||
#define HV_X64_MSR_SVERSION 0x40000081
|
||||
#define HV_X64_MSR_SIEFP 0x40000082
|
||||
#define HV_X64_MSR_SIMP 0x40000083
|
||||
#define HV_X64_MSR_EOM 0x40000084
|
||||
#define HV_X64_MSR_SINT0 0x40000090
|
||||
#define HV_X64_MSR_SINT1 0x40000091
|
||||
#define HV_X64_MSR_SINT2 0x40000092
|
||||
#define HV_X64_MSR_SINT3 0x40000093
|
||||
#define HV_X64_MSR_SINT4 0x40000094
|
||||
#define HV_X64_MSR_SINT5 0x40000095
|
||||
#define HV_X64_MSR_SINT6 0x40000096
|
||||
#define HV_X64_MSR_SINT7 0x40000097
|
||||
#define HV_X64_MSR_SINT8 0x40000098
|
||||
#define HV_X64_MSR_SINT9 0x40000099
|
||||
#define HV_X64_MSR_SINT10 0x4000009A
|
||||
#define HV_X64_MSR_SINT11 0x4000009B
|
||||
#define HV_X64_MSR_SINT12 0x4000009C
|
||||
#define HV_X64_MSR_SINT13 0x4000009D
|
||||
#define HV_X64_MSR_SINT14 0x4000009E
|
||||
#define HV_X64_MSR_SINT15 0x4000009F
|
||||
|
||||
/*
|
||||
* Synthetic Timer MSRs. Four timers per vcpu.
|
||||
*/
|
||||
#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
|
||||
#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
|
||||
#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
|
||||
#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
|
||||
#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
|
||||
#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
|
||||
#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
|
||||
#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
|
||||
|
||||
/* Hyper-V guest crash notification MSR's */
|
||||
#define HV_X64_MSR_CRASH_P0 0x40000100
|
||||
#define HV_X64_MSR_CRASH_P1 0x40000101
|
||||
#define HV_X64_MSR_CRASH_P2 0x40000102
|
||||
#define HV_X64_MSR_CRASH_P3 0x40000103
|
||||
#define HV_X64_MSR_CRASH_P4 0x40000104
|
||||
#define HV_X64_MSR_CRASH_CTL 0x40000105
|
||||
#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63)
|
||||
#define HV_X64_MSR_CRASH_PARAMS \
|
||||
(1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
|
||||
|
||||
#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
|
||||
#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
|
||||
#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
|
||||
(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
|
||||
|
||||
/* Declare the various hypercall operations. */
|
||||
#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
|
||||
#define HVCALL_POST_MESSAGE 0x005c
|
||||
#define HVCALL_SIGNAL_EVENT 0x005d
|
||||
|
||||
#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001
|
||||
#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12
|
||||
#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
|
||||
(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
|
||||
|
||||
#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001
|
||||
#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
|
||||
|
||||
#define HV_PROCESSOR_POWER_STATE_C0 0
|
||||
#define HV_PROCESSOR_POWER_STATE_C1 1
|
||||
#define HV_PROCESSOR_POWER_STATE_C2 2
|
||||
#define HV_PROCESSOR_POWER_STATE_C3 3
|
||||
|
||||
/* hypercall status code */
|
||||
#define HV_STATUS_SUCCESS 0
|
||||
#define HV_STATUS_INVALID_HYPERCALL_CODE 2
|
||||
#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
|
||||
#define HV_STATUS_INVALID_ALIGNMENT 4
|
||||
#define HV_STATUS_INSUFFICIENT_MEMORY 11
|
||||
#define HV_STATUS_INVALID_CONNECTION_ID 18
|
||||
#define HV_STATUS_INSUFFICIENT_BUFFERS 19
|
||||
|
||||
typedef struct _HV_REFERENCE_TSC_PAGE {
|
||||
__u32 tsc_sequence;
|
||||
__u32 res1;
|
||||
__u64 tsc_scale;
|
||||
__s64 tsc_offset;
|
||||
} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
|
||||
|
||||
/* Define the number of synthetic interrupt sources. */
|
||||
#define HV_SYNIC_SINT_COUNT (16)
|
||||
/* Define the expected SynIC version. */
|
||||
#define HV_SYNIC_VERSION_1 (0x1)
|
||||
|
||||
#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0)
|
||||
#define HV_SYNIC_SIMP_ENABLE (1ULL << 0)
|
||||
#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0)
|
||||
#define HV_SYNIC_SINT_MASKED (1ULL << 16)
|
||||
#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17)
|
||||
#define HV_SYNIC_SINT_VECTOR_MASK (0xFF)
|
||||
|
||||
#define HV_SYNIC_STIMER_COUNT (4)
|
||||
|
||||
/* Define synthetic interrupt controller message constants. */
|
||||
#define HV_MESSAGE_SIZE (256)
|
||||
#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
|
||||
#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
|
||||
|
||||
/* Define hypervisor message types. */
|
||||
enum hv_message_type {
|
||||
HVMSG_NONE = 0x00000000,
|
||||
|
||||
/* Memory access messages. */
|
||||
HVMSG_UNMAPPED_GPA = 0x80000000,
|
||||
HVMSG_GPA_INTERCEPT = 0x80000001,
|
||||
|
||||
/* Timer notification messages. */
|
||||
HVMSG_TIMER_EXPIRED = 0x80000010,
|
||||
|
||||
/* Error messages. */
|
||||
HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
|
||||
HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
|
||||
HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
|
||||
|
||||
/* Trace buffer complete messages. */
|
||||
HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
|
||||
|
||||
/* Platform-specific processor intercept messages. */
|
||||
HVMSG_X64_IOPORT_INTERCEPT = 0x80010000,
|
||||
HVMSG_X64_MSR_INTERCEPT = 0x80010001,
|
||||
HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
|
||||
HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
|
||||
HVMSG_X64_APIC_EOI = 0x80010004,
|
||||
HVMSG_X64_LEGACY_FP_ERROR = 0x80010005
|
||||
};
|
||||
|
||||
/* Define synthetic interrupt controller message flags. */
|
||||
union hv_message_flags {
|
||||
__u8 asu8;
|
||||
struct {
|
||||
__u8 msg_pending:1;
|
||||
__u8 reserved:7;
|
||||
};
|
||||
};
|
||||
|
||||
/* Define port identifier type. */
|
||||
union hv_port_id {
|
||||
__u32 asu32;
|
||||
struct {
|
||||
__u32 id:24;
|
||||
__u32 reserved:8;
|
||||
} u;
|
||||
};
|
||||
|
||||
/* Define synthetic interrupt controller message header. */
|
||||
struct hv_message_header {
|
||||
__u32 message_type;
|
||||
__u8 payload_size;
|
||||
union hv_message_flags message_flags;
|
||||
__u8 reserved[2];
|
||||
union {
|
||||
__u64 sender;
|
||||
union hv_port_id port;
|
||||
};
|
||||
};
|
||||
|
||||
/* Define synthetic interrupt controller message format. */
|
||||
struct hv_message {
|
||||
struct hv_message_header header;
|
||||
union {
|
||||
__u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
|
||||
} u;
|
||||
};
|
||||
|
||||
/* Define the synthetic interrupt message page layout. */
|
||||
struct hv_message_page {
|
||||
struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
|
||||
};
|
||||
|
||||
/* Define timer message payload structure. */
|
||||
struct hv_timer_message_payload {
|
||||
__u32 timer_index;
|
||||
__u32 reserved;
|
||||
__u64 expiration_time; /* When the timer expired */
|
||||
__u64 delivery_time; /* When the message was delivered */
|
||||
};
|
||||
|
||||
#define HV_STIMER_ENABLE (1ULL << 0)
|
||||
#define HV_STIMER_PERIODIC (1ULL << 1)
|
||||
#define HV_STIMER_LAZY (1ULL << 2)
|
||||
#define HV_STIMER_AUTOENABLE (1ULL << 3)
|
||||
#define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F)
|
||||
|
||||
#endif
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/ioctl.h>
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/ioctls.h>
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/ipcbuf.h>
|
||||
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Include file for the interface to IST BIOS
|
||||
* Copyright 2002 Andy Grover <andrew.grover@intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2, or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*/
|
||||
#ifndef _ASM_X86_IST_H
|
||||
#define _ASM_X86_IST_H
|
||||
|
||||
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct ist_info {
|
||||
__u32 signature;
|
||||
__u32 command;
|
||||
__u32 event;
|
||||
__u32 perf_level;
|
||||
};
|
||||
|
||||
#endif /* _ASM_X86_IST_H */
|
||||
@ -0,0 +1,360 @@
|
||||
#ifndef _ASM_X86_KVM_H
|
||||
#define _ASM_X86_KVM_H
|
||||
|
||||
/*
|
||||
* KVM x86 specific structures and definitions
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
#define DE_VECTOR 0
|
||||
#define DB_VECTOR 1
|
||||
#define BP_VECTOR 3
|
||||
#define OF_VECTOR 4
|
||||
#define BR_VECTOR 5
|
||||
#define UD_VECTOR 6
|
||||
#define NM_VECTOR 7
|
||||
#define DF_VECTOR 8
|
||||
#define TS_VECTOR 10
|
||||
#define NP_VECTOR 11
|
||||
#define SS_VECTOR 12
|
||||
#define GP_VECTOR 13
|
||||
#define PF_VECTOR 14
|
||||
#define MF_VECTOR 16
|
||||
#define AC_VECTOR 17
|
||||
#define MC_VECTOR 18
|
||||
#define XM_VECTOR 19
|
||||
#define VE_VECTOR 20
|
||||
|
||||
/* Select x86 specific features in <linux/kvm.h> */
|
||||
#define __KVM_HAVE_PIT
|
||||
#define __KVM_HAVE_IOAPIC
|
||||
#define __KVM_HAVE_IRQ_LINE
|
||||
#define __KVM_HAVE_MSI
|
||||
#define __KVM_HAVE_USER_NMI
|
||||
#define __KVM_HAVE_GUEST_DEBUG
|
||||
#define __KVM_HAVE_MSIX
|
||||
#define __KVM_HAVE_MCE
|
||||
#define __KVM_HAVE_PIT_STATE2
|
||||
#define __KVM_HAVE_XEN_HVM
|
||||
#define __KVM_HAVE_VCPU_EVENTS
|
||||
#define __KVM_HAVE_DEBUGREGS
|
||||
#define __KVM_HAVE_XSAVE
|
||||
#define __KVM_HAVE_XCRS
|
||||
#define __KVM_HAVE_READONLY_MEM
|
||||
|
||||
/* Architectural interrupt line count. */
|
||||
#define KVM_NR_INTERRUPTS 256
|
||||
|
||||
struct kvm_memory_alias {
|
||||
__u32 slot; /* this has a different namespace than memory slots */
|
||||
__u32 flags;
|
||||
__u64 guest_phys_addr;
|
||||
__u64 memory_size;
|
||||
__u64 target_phys_addr;
|
||||
};
|
||||
|
||||
/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
|
||||
struct kvm_pic_state {
|
||||
__u8 last_irr; /* edge detection */
|
||||
__u8 irr; /* interrupt request register */
|
||||
__u8 imr; /* interrupt mask register */
|
||||
__u8 isr; /* interrupt service register */
|
||||
__u8 priority_add; /* highest irq priority */
|
||||
__u8 irq_base;
|
||||
__u8 read_reg_select;
|
||||
__u8 poll;
|
||||
__u8 special_mask;
|
||||
__u8 init_state;
|
||||
__u8 auto_eoi;
|
||||
__u8 rotate_on_auto_eoi;
|
||||
__u8 special_fully_nested_mode;
|
||||
__u8 init4; /* true if 4 byte init */
|
||||
__u8 elcr; /* PIIX edge/trigger selection */
|
||||
__u8 elcr_mask;
|
||||
};
|
||||
|
||||
#define KVM_IOAPIC_NUM_PINS 24
|
||||
struct kvm_ioapic_state {
|
||||
__u64 base_address;
|
||||
__u32 ioregsel;
|
||||
__u32 id;
|
||||
__u32 irr;
|
||||
__u32 pad;
|
||||
union {
|
||||
__u64 bits;
|
||||
struct {
|
||||
__u8 vector;
|
||||
__u8 delivery_mode:3;
|
||||
__u8 dest_mode:1;
|
||||
__u8 delivery_status:1;
|
||||
__u8 polarity:1;
|
||||
__u8 remote_irr:1;
|
||||
__u8 trig_mode:1;
|
||||
__u8 mask:1;
|
||||
__u8 reserve:7;
|
||||
__u8 reserved[4];
|
||||
__u8 dest_id;
|
||||
} fields;
|
||||
} redirtbl[KVM_IOAPIC_NUM_PINS];
|
||||
};
|
||||
|
||||
#define KVM_IRQCHIP_PIC_MASTER 0
|
||||
#define KVM_IRQCHIP_PIC_SLAVE 1
|
||||
#define KVM_IRQCHIP_IOAPIC 2
|
||||
#define KVM_NR_IRQCHIPS 3
|
||||
|
||||
#define KVM_RUN_X86_SMM (1 << 0)
|
||||
|
||||
/* for KVM_GET_REGS and KVM_SET_REGS */
|
||||
struct kvm_regs {
|
||||
/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
|
||||
__u64 rax, rbx, rcx, rdx;
|
||||
__u64 rsi, rdi, rsp, rbp;
|
||||
__u64 r8, r9, r10, r11;
|
||||
__u64 r12, r13, r14, r15;
|
||||
__u64 rip, rflags;
|
||||
};
|
||||
|
||||
/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
|
||||
#define KVM_APIC_REG_SIZE 0x400
|
||||
struct kvm_lapic_state {
|
||||
char regs[KVM_APIC_REG_SIZE];
|
||||
};
|
||||
|
||||
struct kvm_segment {
|
||||
__u64 base;
|
||||
__u32 limit;
|
||||
__u16 selector;
|
||||
__u8 type;
|
||||
__u8 present, dpl, db, s, l, g, avl;
|
||||
__u8 unusable;
|
||||
__u8 padding;
|
||||
};
|
||||
|
||||
struct kvm_dtable {
|
||||
__u64 base;
|
||||
__u16 limit;
|
||||
__u16 padding[3];
|
||||
};
|
||||
|
||||
|
||||
/* for KVM_GET_SREGS and KVM_SET_SREGS */
|
||||
struct kvm_sregs {
|
||||
/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
|
||||
struct kvm_segment cs, ds, es, fs, gs, ss;
|
||||
struct kvm_segment tr, ldt;
|
||||
struct kvm_dtable gdt, idt;
|
||||
__u64 cr0, cr2, cr3, cr4, cr8;
|
||||
__u64 efer;
|
||||
__u64 apic_base;
|
||||
__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
|
||||
};
|
||||
|
||||
/* for KVM_GET_FPU and KVM_SET_FPU */
|
||||
struct kvm_fpu {
|
||||
__u8 fpr[8][16];
|
||||
__u16 fcw;
|
||||
__u16 fsw;
|
||||
__u8 ftwx; /* in fxsave format */
|
||||
__u8 pad1;
|
||||
__u16 last_opcode;
|
||||
__u64 last_ip;
|
||||
__u64 last_dp;
|
||||
__u8 xmm[16][16];
|
||||
__u32 mxcsr;
|
||||
__u32 pad2;
|
||||
};
|
||||
|
||||
struct kvm_msr_entry {
|
||||
__u32 index;
|
||||
__u32 reserved;
|
||||
__u64 data;
|
||||
};
|
||||
|
||||
/* for KVM_GET_MSRS and KVM_SET_MSRS */
|
||||
struct kvm_msrs {
|
||||
__u32 nmsrs; /* number of msrs in entries */
|
||||
__u32 pad;
|
||||
|
||||
struct kvm_msr_entry entries[0];
|
||||
};
|
||||
|
||||
/* for KVM_GET_MSR_INDEX_LIST */
|
||||
struct kvm_msr_list {
|
||||
__u32 nmsrs; /* number of msrs in entries */
|
||||
__u32 indices[0];
|
||||
};
|
||||
|
||||
|
||||
struct kvm_cpuid_entry {
|
||||
__u32 function;
|
||||
__u32 eax;
|
||||
__u32 ebx;
|
||||
__u32 ecx;
|
||||
__u32 edx;
|
||||
__u32 padding;
|
||||
};
|
||||
|
||||
/* for KVM_SET_CPUID */
|
||||
struct kvm_cpuid {
|
||||
__u32 nent;
|
||||
__u32 padding;
|
||||
struct kvm_cpuid_entry entries[0];
|
||||
};
|
||||
|
||||
struct kvm_cpuid_entry2 {
|
||||
__u32 function;
|
||||
__u32 index;
|
||||
__u32 flags;
|
||||
__u32 eax;
|
||||
__u32 ebx;
|
||||
__u32 ecx;
|
||||
__u32 edx;
|
||||
__u32 padding[3];
|
||||
};
|
||||
|
||||
#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX BIT(0)
|
||||
#define KVM_CPUID_FLAG_STATEFUL_FUNC BIT(1)
|
||||
#define KVM_CPUID_FLAG_STATE_READ_NEXT BIT(2)
|
||||
|
||||
/* for KVM_SET_CPUID2 */
|
||||
struct kvm_cpuid2 {
|
||||
__u32 nent;
|
||||
__u32 padding;
|
||||
struct kvm_cpuid_entry2 entries[0];
|
||||
};
|
||||
|
||||
/* for KVM_GET_PIT and KVM_SET_PIT */
|
||||
struct kvm_pit_channel_state {
|
||||
__u32 count; /* can be 65536 */
|
||||
__u16 latched_count;
|
||||
__u8 count_latched;
|
||||
__u8 status_latched;
|
||||
__u8 status;
|
||||
__u8 read_state;
|
||||
__u8 write_state;
|
||||
__u8 write_latch;
|
||||
__u8 rw_mode;
|
||||
__u8 mode;
|
||||
__u8 bcd;
|
||||
__u8 gate;
|
||||
__s64 count_load_time;
|
||||
};
|
||||
|
||||
struct kvm_debug_exit_arch {
|
||||
__u32 exception;
|
||||
__u32 pad;
|
||||
__u64 pc;
|
||||
__u64 dr6;
|
||||
__u64 dr7;
|
||||
};
|
||||
|
||||
#define KVM_GUESTDBG_USE_SW_BP 0x00010000
|
||||
#define KVM_GUESTDBG_USE_HW_BP 0x00020000
|
||||
#define KVM_GUESTDBG_INJECT_DB 0x00040000
|
||||
#define KVM_GUESTDBG_INJECT_BP 0x00080000
|
||||
|
||||
/* for KVM_SET_GUEST_DEBUG */
|
||||
struct kvm_guest_debug_arch {
|
||||
__u64 debugreg[8];
|
||||
};
|
||||
|
||||
struct kvm_pit_state {
|
||||
struct kvm_pit_channel_state channels[3];
|
||||
};
|
||||
|
||||
#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
|
||||
|
||||
struct kvm_pit_state2 {
|
||||
struct kvm_pit_channel_state channels[3];
|
||||
__u32 flags;
|
||||
__u32 reserved[9];
|
||||
};
|
||||
|
||||
struct kvm_reinject_control {
|
||||
__u8 pit_reinject;
|
||||
__u8 reserved[31];
|
||||
};
|
||||
|
||||
/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
|
||||
#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
|
||||
#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
|
||||
#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
|
||||
#define KVM_VCPUEVENT_VALID_SMM 0x00000008
|
||||
|
||||
/* Interrupt shadow states */
|
||||
#define KVM_X86_SHADOW_INT_MOV_SS 0x01
|
||||
#define KVM_X86_SHADOW_INT_STI 0x02
|
||||
|
||||
/* for KVM_GET/SET_VCPU_EVENTS */
|
||||
struct kvm_vcpu_events {
|
||||
struct {
|
||||
__u8 injected;
|
||||
__u8 nr;
|
||||
__u8 has_error_code;
|
||||
__u8 pad;
|
||||
__u32 error_code;
|
||||
} exception;
|
||||
struct {
|
||||
__u8 injected;
|
||||
__u8 nr;
|
||||
__u8 soft;
|
||||
__u8 shadow;
|
||||
} interrupt;
|
||||
struct {
|
||||
__u8 injected;
|
||||
__u8 pending;
|
||||
__u8 masked;
|
||||
__u8 pad;
|
||||
} nmi;
|
||||
__u32 sipi_vector;
|
||||
__u32 flags;
|
||||
struct {
|
||||
__u8 smm;
|
||||
__u8 pending;
|
||||
__u8 smm_inside_nmi;
|
||||
__u8 latched_init;
|
||||
} smi;
|
||||
__u32 reserved[9];
|
||||
};
|
||||
|
||||
/* for KVM_GET/SET_DEBUGREGS */
|
||||
struct kvm_debugregs {
|
||||
__u64 db[4];
|
||||
__u64 dr6;
|
||||
__u64 dr7;
|
||||
__u64 flags;
|
||||
__u64 reserved[9];
|
||||
};
|
||||
|
||||
/* for KVM_CAP_XSAVE */
|
||||
struct kvm_xsave {
|
||||
__u32 region[1024];
|
||||
};
|
||||
|
||||
#define KVM_MAX_XCRS 16
|
||||
|
||||
struct kvm_xcr {
|
||||
__u32 xcr;
|
||||
__u32 reserved;
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
struct kvm_xcrs {
|
||||
__u32 nr_xcrs;
|
||||
__u32 flags;
|
||||
struct kvm_xcr xcrs[KVM_MAX_XCRS];
|
||||
__u64 padding[16];
|
||||
};
|
||||
|
||||
/* definition of registers in kvm_run */
|
||||
struct kvm_sync_regs {
|
||||
};
|
||||
|
||||
#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0)
|
||||
#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1)
|
||||
|
||||
#endif /* _ASM_X86_KVM_H */
|
||||
@ -0,0 +1,101 @@
|
||||
#ifndef _ASM_X86_KVM_PARA_H
|
||||
#define _ASM_X86_KVM_PARA_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/hyperv.h>
|
||||
|
||||
/* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx. It
|
||||
* should be used to determine that a VM is running under KVM.
|
||||
*/
|
||||
#define KVM_CPUID_SIGNATURE 0x40000000
|
||||
|
||||
/* This CPUID returns a feature bitmap in eax. Before enabling a particular
|
||||
* paravirtualization, the appropriate feature bit should be checked.
|
||||
*/
|
||||
#define KVM_CPUID_FEATURES 0x40000001
|
||||
#define KVM_FEATURE_CLOCKSOURCE 0
|
||||
#define KVM_FEATURE_NOP_IO_DELAY 1
|
||||
#define KVM_FEATURE_MMU_OP 2
|
||||
/* This indicates that the new set of kvmclock msrs
|
||||
* are available. The use of 0x11 and 0x12 is deprecated
|
||||
*/
|
||||
#define KVM_FEATURE_CLOCKSOURCE2 3
|
||||
#define KVM_FEATURE_ASYNC_PF 4
|
||||
#define KVM_FEATURE_STEAL_TIME 5
|
||||
#define KVM_FEATURE_PV_EOI 6
|
||||
#define KVM_FEATURE_PV_UNHALT 7
|
||||
|
||||
/* The last 8 bits are used to indicate how to interpret the flags field
|
||||
* in pvclock structure. If no bits are set, all flags are ignored.
|
||||
*/
|
||||
#define KVM_FEATURE_CLOCKSOURCE_STABLE_BIT 24
|
||||
|
||||
#define MSR_KVM_WALL_CLOCK 0x11
|
||||
#define MSR_KVM_SYSTEM_TIME 0x12
|
||||
|
||||
#define KVM_MSR_ENABLED 1
|
||||
/* Custom MSRs falls in the range 0x4b564d00-0x4b564dff */
|
||||
#define MSR_KVM_WALL_CLOCK_NEW 0x4b564d00
|
||||
#define MSR_KVM_SYSTEM_TIME_NEW 0x4b564d01
|
||||
#define MSR_KVM_ASYNC_PF_EN 0x4b564d02
|
||||
#define MSR_KVM_STEAL_TIME 0x4b564d03
|
||||
#define MSR_KVM_PV_EOI_EN 0x4b564d04
|
||||
|
||||
struct kvm_steal_time {
|
||||
__u64 steal;
|
||||
__u32 version;
|
||||
__u32 flags;
|
||||
__u32 pad[12];
|
||||
};
|
||||
|
||||
#define KVM_STEAL_ALIGNMENT_BITS 5
|
||||
#define KVM_STEAL_VALID_BITS ((-1ULL << (KVM_STEAL_ALIGNMENT_BITS + 1)))
|
||||
#define KVM_STEAL_RESERVED_MASK (((1 << KVM_STEAL_ALIGNMENT_BITS) - 1 ) << 1)
|
||||
|
||||
#define KVM_MAX_MMU_OP_BATCH 32
|
||||
|
||||
#define KVM_ASYNC_PF_ENABLED (1 << 0)
|
||||
#define KVM_ASYNC_PF_SEND_ALWAYS (1 << 1)
|
||||
|
||||
/* Operations for KVM_HC_MMU_OP */
|
||||
#define KVM_MMU_OP_WRITE_PTE 1
|
||||
#define KVM_MMU_OP_FLUSH_TLB 2
|
||||
#define KVM_MMU_OP_RELEASE_PT 3
|
||||
|
||||
/* Payload for KVM_HC_MMU_OP */
|
||||
struct kvm_mmu_op_header {
|
||||
__u32 op;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct kvm_mmu_op_write_pte {
|
||||
struct kvm_mmu_op_header header;
|
||||
__u64 pte_phys;
|
||||
__u64 pte_val;
|
||||
};
|
||||
|
||||
struct kvm_mmu_op_flush_tlb {
|
||||
struct kvm_mmu_op_header header;
|
||||
};
|
||||
|
||||
struct kvm_mmu_op_release_pt {
|
||||
struct kvm_mmu_op_header header;
|
||||
__u64 pt_phys;
|
||||
};
|
||||
|
||||
#define KVM_PV_REASON_PAGE_NOT_PRESENT 1
|
||||
#define KVM_PV_REASON_PAGE_READY 2
|
||||
|
||||
struct kvm_vcpu_pv_apf_data {
|
||||
__u32 reason;
|
||||
__u8 pad[60];
|
||||
__u32 enabled;
|
||||
};
|
||||
|
||||
#define KVM_PV_EOI_BIT 0
|
||||
#define KVM_PV_EOI_MASK (0x1 << KVM_PV_EOI_BIT)
|
||||
#define KVM_PV_EOI_ENABLED KVM_PV_EOI_MASK
|
||||
#define KVM_PV_EOI_DISABLED 0x0
|
||||
|
||||
|
||||
#endif /* _ASM_X86_KVM_PARA_H */
|
||||
@ -0,0 +1,16 @@
|
||||
#ifndef _ASM_X86_KVM_PERF_H
|
||||
#define _ASM_X86_KVM_PERF_H
|
||||
|
||||
#include <asm/svm.h>
|
||||
#include <asm/vmx.h>
|
||||
#include <asm/kvm.h>
|
||||
|
||||
#define DECODE_STR_LEN 20
|
||||
|
||||
#define VCPU_ID "vcpu_id"
|
||||
|
||||
#define KVM_ENTRY_TRACE "kvm:kvm_entry"
|
||||
#define KVM_EXIT_TRACE "kvm:kvm_exit"
|
||||
#define KVM_EXIT_REASON "exit_reason"
|
||||
|
||||
#endif /* _ASM_X86_KVM_PERF_H */
|
||||
@ -0,0 +1,47 @@
|
||||
/*
|
||||
* ldt.h
|
||||
*
|
||||
* Definitions of structures used with the modify_ldt system call.
|
||||
*/
|
||||
#ifndef _ASM_X86_LDT_H
|
||||
#define _ASM_X86_LDT_H
|
||||
|
||||
/* Maximum number of LDT entries supported. */
|
||||
#define LDT_ENTRIES 8192
|
||||
/* The size of each LDT entry. */
|
||||
#define LDT_ENTRY_SIZE 8
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/*
|
||||
* Note on 64bit base and limit is ignored and you cannot set DS/ES/CS
|
||||
* not to the default values if you still want to do syscalls. This
|
||||
* call is more for 32bit mode therefore.
|
||||
*/
|
||||
struct user_desc {
|
||||
unsigned int entry_number;
|
||||
unsigned int base_addr;
|
||||
unsigned int limit;
|
||||
unsigned int seg_32bit:1;
|
||||
unsigned int contents:2;
|
||||
unsigned int read_exec_only:1;
|
||||
unsigned int limit_in_pages:1;
|
||||
unsigned int seg_not_present:1;
|
||||
unsigned int useable:1;
|
||||
#ifdef __x86_64__
|
||||
/*
|
||||
* Because this bit is not present in 32-bit user code, user
|
||||
* programs can pass uninitialized values here. Therefore, in
|
||||
* any context in which a user_desc comes from a 32-bit program,
|
||||
* the kernel must act as though lm == 0, regardless of the
|
||||
* actual value.
|
||||
*/
|
||||
unsigned int lm:1;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MODIFY_LDT_CONTENTS_DATA 0
|
||||
#define MODIFY_LDT_CONTENTS_STACK 1
|
||||
#define MODIFY_LDT_CONTENTS_CODE 2
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* _ASM_X86_LDT_H */
|
||||
@ -0,0 +1,35 @@
|
||||
#ifndef _ASM_X86_MCE_H
|
||||
#define _ASM_X86_MCE_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
/* Fields are zero when not available */
|
||||
struct mce {
|
||||
__u64 status;
|
||||
__u64 misc;
|
||||
__u64 addr;
|
||||
__u64 mcgstatus;
|
||||
__u64 ip;
|
||||
__u64 tsc; /* cpu time stamp counter */
|
||||
__u64 time; /* wall time_t when error was detected */
|
||||
__u8 cpuvendor; /* cpu vendor as encoded in system.h */
|
||||
__u8 inject_flags; /* software inject flags */
|
||||
__u8 severity;
|
||||
__u8 usable_addr;
|
||||
__u32 cpuid; /* CPUID 1 EAX */
|
||||
__u8 cs; /* code segment */
|
||||
__u8 bank; /* machine check bank */
|
||||
__u8 cpu; /* cpu number; obsolete; use extcpu now */
|
||||
__u8 finished; /* entry is valid */
|
||||
__u32 extcpu; /* linux cpu number that detected the error */
|
||||
__u32 socketid; /* CPU socket ID */
|
||||
__u32 apicid; /* CPU initial apic ID */
|
||||
__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
|
||||
};
|
||||
|
||||
#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
|
||||
#define MCE_GET_LOG_LEN _IOR('M', 2, int)
|
||||
#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
|
||||
|
||||
#endif /* _ASM_X86_MCE_H */
|
||||
@ -0,0 +1,11 @@
|
||||
#ifndef _ASM_X86_MMAN_H
|
||||
#define _ASM_X86_MMAN_H
|
||||
|
||||
#define MAP_32BIT 0x40 /* only give out 32bit addresses */
|
||||
|
||||
#define MAP_HUGE_2MB (21 << MAP_HUGE_SHIFT)
|
||||
#define MAP_HUGE_1GB (30 << MAP_HUGE_SHIFT)
|
||||
|
||||
#include <asm-generic/mman.h>
|
||||
|
||||
#endif /* _ASM_X86_MMAN_H */
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/msgbuf.h>
|
||||
@ -0,0 +1,702 @@
|
||||
#ifndef _ASM_X86_MSR_INDEX_H
|
||||
#define _ASM_X86_MSR_INDEX_H
|
||||
|
||||
/* CPU model specific register (MSR) numbers */
|
||||
|
||||
/* x86-64 specific MSRs */
|
||||
#define MSR_EFER 0xc0000080 /* extended feature register */
|
||||
#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
|
||||
#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
|
||||
#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
|
||||
#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
|
||||
#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
|
||||
#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
|
||||
#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
|
||||
#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
|
||||
|
||||
/* EFER bits: */
|
||||
#define _EFER_SCE 0 /* SYSCALL/SYSRET */
|
||||
#define _EFER_LME 8 /* Long mode enable */
|
||||
#define _EFER_LMA 10 /* Long mode active (read-only) */
|
||||
#define _EFER_NX 11 /* No execute enable */
|
||||
#define _EFER_SVME 12 /* Enable virtualization */
|
||||
#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
|
||||
#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
|
||||
|
||||
#define EFER_SCE (1<<_EFER_SCE)
|
||||
#define EFER_LME (1<<_EFER_LME)
|
||||
#define EFER_LMA (1<<_EFER_LMA)
|
||||
#define EFER_NX (1<<_EFER_NX)
|
||||
#define EFER_SVME (1<<_EFER_SVME)
|
||||
#define EFER_LMSLE (1<<_EFER_LMSLE)
|
||||
#define EFER_FFXSR (1<<_EFER_FFXSR)
|
||||
|
||||
/* Intel MSRs. Some also available on other CPUs */
|
||||
#define MSR_IA32_PERFCTR0 0x000000c1
|
||||
#define MSR_IA32_PERFCTR1 0x000000c2
|
||||
#define MSR_FSB_FREQ 0x000000cd
|
||||
#define MSR_PLATFORM_INFO 0x000000ce
|
||||
|
||||
#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
|
||||
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
|
||||
#define NHM_C1_AUTO_DEMOTE (1UL << 26)
|
||||
#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
|
||||
#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
|
||||
#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
|
||||
|
||||
#define MSR_MTRRcap 0x000000fe
|
||||
#define MSR_IA32_BBL_CR_CTL 0x00000119
|
||||
#define MSR_IA32_BBL_CR_CTL3 0x0000011e
|
||||
|
||||
#define MSR_IA32_SYSENTER_CS 0x00000174
|
||||
#define MSR_IA32_SYSENTER_ESP 0x00000175
|
||||
#define MSR_IA32_SYSENTER_EIP 0x00000176
|
||||
|
||||
#define MSR_IA32_MCG_CAP 0x00000179
|
||||
#define MSR_IA32_MCG_STATUS 0x0000017a
|
||||
#define MSR_IA32_MCG_CTL 0x0000017b
|
||||
#define MSR_IA32_MCG_EXT_CTL 0x000004d0
|
||||
|
||||
#define MSR_OFFCORE_RSP_0 0x000001a6
|
||||
#define MSR_OFFCORE_RSP_1 0x000001a7
|
||||
#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
|
||||
#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
|
||||
#define MSR_TURBO_RATIO_LIMIT 0x000001ad
|
||||
#define MSR_TURBO_RATIO_LIMIT1 0x000001ae
|
||||
#define MSR_TURBO_RATIO_LIMIT2 0x000001af
|
||||
|
||||
#define MSR_LBR_SELECT 0x000001c8
|
||||
#define MSR_LBR_TOS 0x000001c9
|
||||
#define MSR_LBR_NHM_FROM 0x00000680
|
||||
#define MSR_LBR_NHM_TO 0x000006c0
|
||||
#define MSR_LBR_CORE_FROM 0x00000040
|
||||
#define MSR_LBR_CORE_TO 0x00000060
|
||||
|
||||
#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
|
||||
#define LBR_INFO_MISPRED BIT_ULL(63)
|
||||
#define LBR_INFO_IN_TX BIT_ULL(62)
|
||||
#define LBR_INFO_ABORT BIT_ULL(61)
|
||||
#define LBR_INFO_CYCLES 0xffff
|
||||
|
||||
#define MSR_IA32_PEBS_ENABLE 0x000003f1
|
||||
#define MSR_IA32_DS_AREA 0x00000600
|
||||
#define MSR_IA32_PERF_CAPABILITIES 0x00000345
|
||||
#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
|
||||
|
||||
#define MSR_IA32_RTIT_CTL 0x00000570
|
||||
#define RTIT_CTL_TRACEEN BIT(0)
|
||||
#define RTIT_CTL_CYCLEACC BIT(1)
|
||||
#define RTIT_CTL_OS BIT(2)
|
||||
#define RTIT_CTL_USR BIT(3)
|
||||
#define RTIT_CTL_CR3EN BIT(7)
|
||||
#define RTIT_CTL_TOPA BIT(8)
|
||||
#define RTIT_CTL_MTC_EN BIT(9)
|
||||
#define RTIT_CTL_TSC_EN BIT(10)
|
||||
#define RTIT_CTL_DISRETC BIT(11)
|
||||
#define RTIT_CTL_BRANCH_EN BIT(13)
|
||||
#define RTIT_CTL_MTC_RANGE_OFFSET 14
|
||||
#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
|
||||
#define RTIT_CTL_CYC_THRESH_OFFSET 19
|
||||
#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
|
||||
#define RTIT_CTL_PSB_FREQ_OFFSET 24
|
||||
#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
|
||||
#define MSR_IA32_RTIT_STATUS 0x00000571
|
||||
#define RTIT_STATUS_CONTEXTEN BIT(1)
|
||||
#define RTIT_STATUS_TRIGGEREN BIT(2)
|
||||
#define RTIT_STATUS_ERROR BIT(4)
|
||||
#define RTIT_STATUS_STOPPED BIT(5)
|
||||
#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
|
||||
#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
|
||||
#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
|
||||
|
||||
#define MSR_MTRRfix64K_00000 0x00000250
|
||||
#define MSR_MTRRfix16K_80000 0x00000258
|
||||
#define MSR_MTRRfix16K_A0000 0x00000259
|
||||
#define MSR_MTRRfix4K_C0000 0x00000268
|
||||
#define MSR_MTRRfix4K_C8000 0x00000269
|
||||
#define MSR_MTRRfix4K_D0000 0x0000026a
|
||||
#define MSR_MTRRfix4K_D8000 0x0000026b
|
||||
#define MSR_MTRRfix4K_E0000 0x0000026c
|
||||
#define MSR_MTRRfix4K_E8000 0x0000026d
|
||||
#define MSR_MTRRfix4K_F0000 0x0000026e
|
||||
#define MSR_MTRRfix4K_F8000 0x0000026f
|
||||
#define MSR_MTRRdefType 0x000002ff
|
||||
|
||||
#define MSR_IA32_CR_PAT 0x00000277
|
||||
|
||||
#define MSR_IA32_DEBUGCTLMSR 0x000001d9
|
||||
#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
|
||||
#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
|
||||
#define MSR_IA32_LASTINTFROMIP 0x000001dd
|
||||
#define MSR_IA32_LASTINTTOIP 0x000001de
|
||||
|
||||
/* DEBUGCTLMSR bits (others vary by model): */
|
||||
#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
|
||||
#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
|
||||
#define DEBUGCTLMSR_TR (1UL << 6)
|
||||
#define DEBUGCTLMSR_BTS (1UL << 7)
|
||||
#define DEBUGCTLMSR_BTINT (1UL << 8)
|
||||
#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
|
||||
#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
|
||||
#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
|
||||
|
||||
#define MSR_PEBS_FRONTEND 0x000003f7
|
||||
|
||||
#define MSR_IA32_POWER_CTL 0x000001fc
|
||||
|
||||
#define MSR_IA32_MC0_CTL 0x00000400
|
||||
#define MSR_IA32_MC0_STATUS 0x00000401
|
||||
#define MSR_IA32_MC0_ADDR 0x00000402
|
||||
#define MSR_IA32_MC0_MISC 0x00000403
|
||||
|
||||
/* C-state Residency Counters */
|
||||
#define MSR_PKG_C3_RESIDENCY 0x000003f8
|
||||
#define MSR_PKG_C6_RESIDENCY 0x000003f9
|
||||
#define MSR_PKG_C7_RESIDENCY 0x000003fa
|
||||
#define MSR_CORE_C3_RESIDENCY 0x000003fc
|
||||
#define MSR_CORE_C6_RESIDENCY 0x000003fd
|
||||
#define MSR_CORE_C7_RESIDENCY 0x000003fe
|
||||
#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
|
||||
#define MSR_PKG_C2_RESIDENCY 0x0000060d
|
||||
#define MSR_PKG_C8_RESIDENCY 0x00000630
|
||||
#define MSR_PKG_C9_RESIDENCY 0x00000631
|
||||
#define MSR_PKG_C10_RESIDENCY 0x00000632
|
||||
|
||||
/* Interrupt Response Limit */
|
||||
#define MSR_PKGC3_IRTL 0x0000060a
|
||||
#define MSR_PKGC6_IRTL 0x0000060b
|
||||
#define MSR_PKGC7_IRTL 0x0000060c
|
||||
#define MSR_PKGC8_IRTL 0x00000633
|
||||
#define MSR_PKGC9_IRTL 0x00000634
|
||||
#define MSR_PKGC10_IRTL 0x00000635
|
||||
|
||||
/* Run Time Average Power Limiting (RAPL) Interface */
|
||||
|
||||
#define MSR_RAPL_POWER_UNIT 0x00000606
|
||||
|
||||
#define MSR_PKG_POWER_LIMIT 0x00000610
|
||||
#define MSR_PKG_ENERGY_STATUS 0x00000611
|
||||
#define MSR_PKG_PERF_STATUS 0x00000613
|
||||
#define MSR_PKG_POWER_INFO 0x00000614
|
||||
|
||||
#define MSR_DRAM_POWER_LIMIT 0x00000618
|
||||
#define MSR_DRAM_ENERGY_STATUS 0x00000619
|
||||
#define MSR_DRAM_PERF_STATUS 0x0000061b
|
||||
#define MSR_DRAM_POWER_INFO 0x0000061c
|
||||
|
||||
#define MSR_PP0_POWER_LIMIT 0x00000638
|
||||
#define MSR_PP0_ENERGY_STATUS 0x00000639
|
||||
#define MSR_PP0_POLICY 0x0000063a
|
||||
#define MSR_PP0_PERF_STATUS 0x0000063b
|
||||
|
||||
#define MSR_PP1_POWER_LIMIT 0x00000640
|
||||
#define MSR_PP1_ENERGY_STATUS 0x00000641
|
||||
#define MSR_PP1_POLICY 0x00000642
|
||||
|
||||
#define MSR_CONFIG_TDP_NOMINAL 0x00000648
|
||||
#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
|
||||
#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
|
||||
#define MSR_CONFIG_TDP_CONTROL 0x0000064B
|
||||
#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
|
||||
|
||||
#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
|
||||
#define MSR_PKG_ANY_CORE_C0_RES 0x00000659
|
||||
#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
|
||||
#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
|
||||
|
||||
#define MSR_CORE_C1_RES 0x00000660
|
||||
|
||||
#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
|
||||
#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
|
||||
|
||||
#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
|
||||
#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
|
||||
#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
|
||||
|
||||
/* Config TDP MSRs */
|
||||
#define MSR_CONFIG_TDP_NOMINAL 0x00000648
|
||||
#define MSR_CONFIG_TDP_LEVEL1 0x00000649
|
||||
#define MSR_CONFIG_TDP_LEVEL2 0x0000064A
|
||||
#define MSR_CONFIG_TDP_CONTROL 0x0000064B
|
||||
#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
|
||||
|
||||
/* Hardware P state interface */
|
||||
#define MSR_PPERF 0x0000064e
|
||||
#define MSR_PERF_LIMIT_REASONS 0x0000064f
|
||||
#define MSR_PM_ENABLE 0x00000770
|
||||
#define MSR_HWP_CAPABILITIES 0x00000771
|
||||
#define MSR_HWP_REQUEST_PKG 0x00000772
|
||||
#define MSR_HWP_INTERRUPT 0x00000773
|
||||
#define MSR_HWP_REQUEST 0x00000774
|
||||
#define MSR_HWP_STATUS 0x00000777
|
||||
|
||||
/* CPUID.6.EAX */
|
||||
#define HWP_BASE_BIT (1<<7)
|
||||
#define HWP_NOTIFICATIONS_BIT (1<<8)
|
||||
#define HWP_ACTIVITY_WINDOW_BIT (1<<9)
|
||||
#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
|
||||
#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
|
||||
|
||||
/* IA32_HWP_CAPABILITIES */
|
||||
#define HWP_HIGHEST_PERF(x) (x & 0xff)
|
||||
#define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8)
|
||||
#define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16)
|
||||
#define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24)
|
||||
|
||||
/* IA32_HWP_REQUEST */
|
||||
#define HWP_MIN_PERF(x) (x & 0xff)
|
||||
#define HWP_MAX_PERF(x) ((x & 0xff) << 8)
|
||||
#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
|
||||
#define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24)
|
||||
#define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32)
|
||||
#define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42)
|
||||
|
||||
/* IA32_HWP_STATUS */
|
||||
#define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
|
||||
#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
|
||||
|
||||
/* IA32_HWP_INTERRUPT */
|
||||
#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
|
||||
#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
|
||||
|
||||
#define MSR_AMD64_MC0_MASK 0xc0010044
|
||||
|
||||
#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
|
||||
#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
|
||||
#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
|
||||
#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
|
||||
|
||||
#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
|
||||
|
||||
/* These are consecutive and not in the normal 4er MCE bank block */
|
||||
#define MSR_IA32_MC0_CTL2 0x00000280
|
||||
#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
|
||||
|
||||
#define MSR_P6_PERFCTR0 0x000000c1
|
||||
#define MSR_P6_PERFCTR1 0x000000c2
|
||||
#define MSR_P6_EVNTSEL0 0x00000186
|
||||
#define MSR_P6_EVNTSEL1 0x00000187
|
||||
|
||||
#define MSR_KNC_PERFCTR0 0x00000020
|
||||
#define MSR_KNC_PERFCTR1 0x00000021
|
||||
#define MSR_KNC_EVNTSEL0 0x00000028
|
||||
#define MSR_KNC_EVNTSEL1 0x00000029
|
||||
|
||||
/* Alternative perfctr range with full access. */
|
||||
#define MSR_IA32_PMC0 0x000004c1
|
||||
|
||||
/* AMD64 MSRs. Not complete. See the architecture manual for a more
|
||||
complete list. */
|
||||
|
||||
#define MSR_AMD64_PATCH_LEVEL 0x0000008b
|
||||
#define MSR_AMD64_TSC_RATIO 0xc0000104
|
||||
#define MSR_AMD64_NB_CFG 0xc001001f
|
||||
#define MSR_AMD64_PATCH_LOADER 0xc0010020
|
||||
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
|
||||
#define MSR_AMD64_OSVW_STATUS 0xc0010141
|
||||
#define MSR_AMD64_LS_CFG 0xc0011020
|
||||
#define MSR_AMD64_DC_CFG 0xc0011022
|
||||
#define MSR_AMD64_BU_CFG2 0xc001102a
|
||||
#define MSR_AMD64_IBSFETCHCTL 0xc0011030
|
||||
#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
|
||||
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
|
||||
#define MSR_AMD64_IBSFETCH_REG_COUNT 3
|
||||
#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
|
||||
#define MSR_AMD64_IBSOPCTL 0xc0011033
|
||||
#define MSR_AMD64_IBSOPRIP 0xc0011034
|
||||
#define MSR_AMD64_IBSOPDATA 0xc0011035
|
||||
#define MSR_AMD64_IBSOPDATA2 0xc0011036
|
||||
#define MSR_AMD64_IBSOPDATA3 0xc0011037
|
||||
#define MSR_AMD64_IBSDCLINAD 0xc0011038
|
||||
#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
|
||||
#define MSR_AMD64_IBSOP_REG_COUNT 7
|
||||
#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
|
||||
#define MSR_AMD64_IBSCTL 0xc001103a
|
||||
#define MSR_AMD64_IBSBRTARGET 0xc001103b
|
||||
#define MSR_AMD64_IBSOPDATA4 0xc001103d
|
||||
#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
|
||||
|
||||
/* Fam 16h MSRs */
|
||||
#define MSR_F16H_L2I_PERF_CTL 0xc0010230
|
||||
#define MSR_F16H_L2I_PERF_CTR 0xc0010231
|
||||
#define MSR_F16H_DR1_ADDR_MASK 0xc0011019
|
||||
#define MSR_F16H_DR2_ADDR_MASK 0xc001101a
|
||||
#define MSR_F16H_DR3_ADDR_MASK 0xc001101b
|
||||
#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
|
||||
|
||||
/* Fam 15h MSRs */
|
||||
#define MSR_F15H_PERF_CTL 0xc0010200
|
||||
#define MSR_F15H_PERF_CTR 0xc0010201
|
||||
#define MSR_F15H_NB_PERF_CTL 0xc0010240
|
||||
#define MSR_F15H_NB_PERF_CTR 0xc0010241
|
||||
|
||||
/* Fam 10h MSRs */
|
||||
#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
|
||||
#define FAM10H_MMIO_CONF_ENABLE (1<<0)
|
||||
#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
|
||||
#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
|
||||
#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
|
||||
#define FAM10H_MMIO_CONF_BASE_SHIFT 20
|
||||
#define MSR_FAM10H_NODE_ID 0xc001100c
|
||||
|
||||
/* K8 MSRs */
|
||||
#define MSR_K8_TOP_MEM1 0xc001001a
|
||||
#define MSR_K8_TOP_MEM2 0xc001001d
|
||||
#define MSR_K8_SYSCFG 0xc0010010
|
||||
#define MSR_K8_INT_PENDING_MSG 0xc0010055
|
||||
/* C1E active bits in int pending message */
|
||||
#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
|
||||
#define MSR_K8_TSEG_ADDR 0xc0010112
|
||||
#define MSR_K8_TSEG_MASK 0xc0010113
|
||||
#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
|
||||
#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
|
||||
#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
|
||||
|
||||
/* K7 MSRs */
|
||||
#define MSR_K7_EVNTSEL0 0xc0010000
|
||||
#define MSR_K7_PERFCTR0 0xc0010004
|
||||
#define MSR_K7_EVNTSEL1 0xc0010001
|
||||
#define MSR_K7_PERFCTR1 0xc0010005
|
||||
#define MSR_K7_EVNTSEL2 0xc0010002
|
||||
#define MSR_K7_PERFCTR2 0xc0010006
|
||||
#define MSR_K7_EVNTSEL3 0xc0010003
|
||||
#define MSR_K7_PERFCTR3 0xc0010007
|
||||
#define MSR_K7_CLK_CTL 0xc001001b
|
||||
#define MSR_K7_HWCR 0xc0010015
|
||||
#define MSR_K7_FID_VID_CTL 0xc0010041
|
||||
#define MSR_K7_FID_VID_STATUS 0xc0010042
|
||||
|
||||
/* K6 MSRs */
|
||||
#define MSR_K6_WHCR 0xc0000082
|
||||
#define MSR_K6_UWCCR 0xc0000085
|
||||
#define MSR_K6_EPMR 0xc0000086
|
||||
#define MSR_K6_PSOR 0xc0000087
|
||||
#define MSR_K6_PFIR 0xc0000088
|
||||
|
||||
/* Centaur-Hauls/IDT defined MSRs. */
|
||||
#define MSR_IDT_FCR1 0x00000107
|
||||
#define MSR_IDT_FCR2 0x00000108
|
||||
#define MSR_IDT_FCR3 0x00000109
|
||||
#define MSR_IDT_FCR4 0x0000010a
|
||||
|
||||
#define MSR_IDT_MCR0 0x00000110
|
||||
#define MSR_IDT_MCR1 0x00000111
|
||||
#define MSR_IDT_MCR2 0x00000112
|
||||
#define MSR_IDT_MCR3 0x00000113
|
||||
#define MSR_IDT_MCR4 0x00000114
|
||||
#define MSR_IDT_MCR5 0x00000115
|
||||
#define MSR_IDT_MCR6 0x00000116
|
||||
#define MSR_IDT_MCR7 0x00000117
|
||||
#define MSR_IDT_MCR_CTRL 0x00000120
|
||||
|
||||
/* VIA Cyrix defined MSRs*/
|
||||
#define MSR_VIA_FCR 0x00001107
|
||||
#define MSR_VIA_LONGHAUL 0x0000110a
|
||||
#define MSR_VIA_RNG 0x0000110b
|
||||
#define MSR_VIA_BCR2 0x00001147
|
||||
|
||||
/* Transmeta defined MSRs */
|
||||
#define MSR_TMTA_LONGRUN_CTRL 0x80868010
|
||||
#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
|
||||
#define MSR_TMTA_LRTI_READOUT 0x80868018
|
||||
#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
|
||||
|
||||
/* Intel defined MSRs. */
|
||||
#define MSR_IA32_P5_MC_ADDR 0x00000000
|
||||
#define MSR_IA32_P5_MC_TYPE 0x00000001
|
||||
#define MSR_IA32_TSC 0x00000010
|
||||
#define MSR_IA32_PLATFORM_ID 0x00000017
|
||||
#define MSR_IA32_EBL_CR_POWERON 0x0000002a
|
||||
#define MSR_EBC_FREQUENCY_ID 0x0000002c
|
||||
#define MSR_SMI_COUNT 0x00000034
|
||||
#define MSR_IA32_FEATURE_CONTROL 0x0000003a
|
||||
#define MSR_IA32_TSC_ADJUST 0x0000003b
|
||||
#define MSR_IA32_BNDCFGS 0x00000d90
|
||||
|
||||
#define MSR_IA32_XSS 0x00000da0
|
||||
|
||||
#define FEATURE_CONTROL_LOCKED (1<<0)
|
||||
#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
|
||||
#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
|
||||
#define FEATURE_CONTROL_LMCE (1<<20)
|
||||
|
||||
#define MSR_IA32_APICBASE 0x0000001b
|
||||
#define MSR_IA32_APICBASE_BSP (1<<8)
|
||||
#define MSR_IA32_APICBASE_ENABLE (1<<11)
|
||||
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
|
||||
|
||||
#define MSR_IA32_TSCDEADLINE 0x000006e0
|
||||
|
||||
#define MSR_IA32_UCODE_WRITE 0x00000079
|
||||
#define MSR_IA32_UCODE_REV 0x0000008b
|
||||
|
||||
#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
|
||||
#define MSR_IA32_SMBASE 0x0000009e
|
||||
|
||||
#define MSR_IA32_PERF_STATUS 0x00000198
|
||||
#define MSR_IA32_PERF_CTL 0x00000199
|
||||
#define INTEL_PERF_CTL_MASK 0xffff
|
||||
#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
|
||||
#define MSR_AMD_PERF_STATUS 0xc0010063
|
||||
#define MSR_AMD_PERF_CTL 0xc0010062
|
||||
|
||||
#define MSR_IA32_MPERF 0x000000e7
|
||||
#define MSR_IA32_APERF 0x000000e8
|
||||
|
||||
#define MSR_IA32_THERM_CONTROL 0x0000019a
|
||||
#define MSR_IA32_THERM_INTERRUPT 0x0000019b
|
||||
|
||||
#define THERM_INT_HIGH_ENABLE (1 << 0)
|
||||
#define THERM_INT_LOW_ENABLE (1 << 1)
|
||||
#define THERM_INT_PLN_ENABLE (1 << 24)
|
||||
|
||||
#define MSR_IA32_THERM_STATUS 0x0000019c
|
||||
|
||||
#define THERM_STATUS_PROCHOT (1 << 0)
|
||||
#define THERM_STATUS_POWER_LIMIT (1 << 10)
|
||||
|
||||
#define MSR_THERM2_CTL 0x0000019d
|
||||
|
||||
#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
|
||||
|
||||
#define MSR_IA32_MISC_ENABLE 0x000001a0
|
||||
|
||||
#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
|
||||
|
||||
#define MSR_MISC_PWR_MGMT 0x000001aa
|
||||
|
||||
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
|
||||
#define ENERGY_PERF_BIAS_PERFORMANCE 0
|
||||
#define ENERGY_PERF_BIAS_NORMAL 6
|
||||
#define ENERGY_PERF_BIAS_POWERSAVE 15
|
||||
|
||||
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
|
||||
|
||||
#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
|
||||
#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
|
||||
|
||||
#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
|
||||
|
||||
#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
|
||||
#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
|
||||
#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
|
||||
|
||||
/* Thermal Thresholds Support */
|
||||
#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
|
||||
#define THERM_SHIFT_THRESHOLD0 8
|
||||
#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
|
||||
#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
|
||||
#define THERM_SHIFT_THRESHOLD1 16
|
||||
#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
|
||||
#define THERM_STATUS_THRESHOLD0 (1 << 6)
|
||||
#define THERM_LOG_THRESHOLD0 (1 << 7)
|
||||
#define THERM_STATUS_THRESHOLD1 (1 << 8)
|
||||
#define THERM_LOG_THRESHOLD1 (1 << 9)
|
||||
|
||||
/* MISC_ENABLE bits: architectural */
|
||||
#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
|
||||
#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_TCC_BIT 1
|
||||
#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_EMON_BIT 7
|
||||
#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
|
||||
#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
|
||||
#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
|
||||
#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
|
||||
#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
|
||||
#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
|
||||
#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
|
||||
#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
|
||||
|
||||
/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
|
||||
#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
|
||||
#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_TM1_BIT 3
|
||||
#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
|
||||
#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
|
||||
#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
|
||||
#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
|
||||
#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_FERR_BIT 10
|
||||
#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
|
||||
#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_TM2_BIT 13
|
||||
#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
|
||||
#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
|
||||
#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
|
||||
#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
|
||||
#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
|
||||
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
|
||||
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
|
||||
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
|
||||
|
||||
#define MSR_IA32_TSC_DEADLINE 0x000006E0
|
||||
|
||||
/* P4/Xeon+ specific */
|
||||
#define MSR_IA32_MCG_EAX 0x00000180
|
||||
#define MSR_IA32_MCG_EBX 0x00000181
|
||||
#define MSR_IA32_MCG_ECX 0x00000182
|
||||
#define MSR_IA32_MCG_EDX 0x00000183
|
||||
#define MSR_IA32_MCG_ESI 0x00000184
|
||||
#define MSR_IA32_MCG_EDI 0x00000185
|
||||
#define MSR_IA32_MCG_EBP 0x00000186
|
||||
#define MSR_IA32_MCG_ESP 0x00000187
|
||||
#define MSR_IA32_MCG_EFLAGS 0x00000188
|
||||
#define MSR_IA32_MCG_EIP 0x00000189
|
||||
#define MSR_IA32_MCG_RESERVED 0x0000018a
|
||||
|
||||
/* Pentium IV performance counter MSRs */
|
||||
#define MSR_P4_BPU_PERFCTR0 0x00000300
|
||||
#define MSR_P4_BPU_PERFCTR1 0x00000301
|
||||
#define MSR_P4_BPU_PERFCTR2 0x00000302
|
||||
#define MSR_P4_BPU_PERFCTR3 0x00000303
|
||||
#define MSR_P4_MS_PERFCTR0 0x00000304
|
||||
#define MSR_P4_MS_PERFCTR1 0x00000305
|
||||
#define MSR_P4_MS_PERFCTR2 0x00000306
|
||||
#define MSR_P4_MS_PERFCTR3 0x00000307
|
||||
#define MSR_P4_FLAME_PERFCTR0 0x00000308
|
||||
#define MSR_P4_FLAME_PERFCTR1 0x00000309
|
||||
#define MSR_P4_FLAME_PERFCTR2 0x0000030a
|
||||
#define MSR_P4_FLAME_PERFCTR3 0x0000030b
|
||||
#define MSR_P4_IQ_PERFCTR0 0x0000030c
|
||||
#define MSR_P4_IQ_PERFCTR1 0x0000030d
|
||||
#define MSR_P4_IQ_PERFCTR2 0x0000030e
|
||||
#define MSR_P4_IQ_PERFCTR3 0x0000030f
|
||||
#define MSR_P4_IQ_PERFCTR4 0x00000310
|
||||
#define MSR_P4_IQ_PERFCTR5 0x00000311
|
||||
#define MSR_P4_BPU_CCCR0 0x00000360
|
||||
#define MSR_P4_BPU_CCCR1 0x00000361
|
||||
#define MSR_P4_BPU_CCCR2 0x00000362
|
||||
#define MSR_P4_BPU_CCCR3 0x00000363
|
||||
#define MSR_P4_MS_CCCR0 0x00000364
|
||||
#define MSR_P4_MS_CCCR1 0x00000365
|
||||
#define MSR_P4_MS_CCCR2 0x00000366
|
||||
#define MSR_P4_MS_CCCR3 0x00000367
|
||||
#define MSR_P4_FLAME_CCCR0 0x00000368
|
||||
#define MSR_P4_FLAME_CCCR1 0x00000369
|
||||
#define MSR_P4_FLAME_CCCR2 0x0000036a
|
||||
#define MSR_P4_FLAME_CCCR3 0x0000036b
|
||||
#define MSR_P4_IQ_CCCR0 0x0000036c
|
||||
#define MSR_P4_IQ_CCCR1 0x0000036d
|
||||
#define MSR_P4_IQ_CCCR2 0x0000036e
|
||||
#define MSR_P4_IQ_CCCR3 0x0000036f
|
||||
#define MSR_P4_IQ_CCCR4 0x00000370
|
||||
#define MSR_P4_IQ_CCCR5 0x00000371
|
||||
#define MSR_P4_ALF_ESCR0 0x000003ca
|
||||
#define MSR_P4_ALF_ESCR1 0x000003cb
|
||||
#define MSR_P4_BPU_ESCR0 0x000003b2
|
||||
#define MSR_P4_BPU_ESCR1 0x000003b3
|
||||
#define MSR_P4_BSU_ESCR0 0x000003a0
|
||||
#define MSR_P4_BSU_ESCR1 0x000003a1
|
||||
#define MSR_P4_CRU_ESCR0 0x000003b8
|
||||
#define MSR_P4_CRU_ESCR1 0x000003b9
|
||||
#define MSR_P4_CRU_ESCR2 0x000003cc
|
||||
#define MSR_P4_CRU_ESCR3 0x000003cd
|
||||
#define MSR_P4_CRU_ESCR4 0x000003e0
|
||||
#define MSR_P4_CRU_ESCR5 0x000003e1
|
||||
#define MSR_P4_DAC_ESCR0 0x000003a8
|
||||
#define MSR_P4_DAC_ESCR1 0x000003a9
|
||||
#define MSR_P4_FIRM_ESCR0 0x000003a4
|
||||
#define MSR_P4_FIRM_ESCR1 0x000003a5
|
||||
#define MSR_P4_FLAME_ESCR0 0x000003a6
|
||||
#define MSR_P4_FLAME_ESCR1 0x000003a7
|
||||
#define MSR_P4_FSB_ESCR0 0x000003a2
|
||||
#define MSR_P4_FSB_ESCR1 0x000003a3
|
||||
#define MSR_P4_IQ_ESCR0 0x000003ba
|
||||
#define MSR_P4_IQ_ESCR1 0x000003bb
|
||||
#define MSR_P4_IS_ESCR0 0x000003b4
|
||||
#define MSR_P4_IS_ESCR1 0x000003b5
|
||||
#define MSR_P4_ITLB_ESCR0 0x000003b6
|
||||
#define MSR_P4_ITLB_ESCR1 0x000003b7
|
||||
#define MSR_P4_IX_ESCR0 0x000003c8
|
||||
#define MSR_P4_IX_ESCR1 0x000003c9
|
||||
#define MSR_P4_MOB_ESCR0 0x000003aa
|
||||
#define MSR_P4_MOB_ESCR1 0x000003ab
|
||||
#define MSR_P4_MS_ESCR0 0x000003c0
|
||||
#define MSR_P4_MS_ESCR1 0x000003c1
|
||||
#define MSR_P4_PMH_ESCR0 0x000003ac
|
||||
#define MSR_P4_PMH_ESCR1 0x000003ad
|
||||
#define MSR_P4_RAT_ESCR0 0x000003bc
|
||||
#define MSR_P4_RAT_ESCR1 0x000003bd
|
||||
#define MSR_P4_SAAT_ESCR0 0x000003ae
|
||||
#define MSR_P4_SAAT_ESCR1 0x000003af
|
||||
#define MSR_P4_SSU_ESCR0 0x000003be
|
||||
#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
|
||||
|
||||
#define MSR_P4_TBPU_ESCR0 0x000003c2
|
||||
#define MSR_P4_TBPU_ESCR1 0x000003c3
|
||||
#define MSR_P4_TC_ESCR0 0x000003c4
|
||||
#define MSR_P4_TC_ESCR1 0x000003c5
|
||||
#define MSR_P4_U2L_ESCR0 0x000003b0
|
||||
#define MSR_P4_U2L_ESCR1 0x000003b1
|
||||
|
||||
#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
|
||||
|
||||
/* Intel Core-based CPU performance counters */
|
||||
#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
|
||||
#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
|
||||
#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
|
||||
#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
|
||||
#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
|
||||
#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
|
||||
#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
|
||||
|
||||
/* Geode defined MSRs */
|
||||
#define MSR_GEODE_BUSCONT_CONF0 0x00001900
|
||||
|
||||
/* Intel VT MSRs */
|
||||
#define MSR_IA32_VMX_BASIC 0x00000480
|
||||
#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
|
||||
#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
|
||||
#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
|
||||
#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
|
||||
#define MSR_IA32_VMX_MISC 0x00000485
|
||||
#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
|
||||
#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
|
||||
#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
|
||||
#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
|
||||
#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
|
||||
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
|
||||
#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
|
||||
#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
|
||||
#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
|
||||
#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
|
||||
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
|
||||
#define MSR_IA32_VMX_VMFUNC 0x00000491
|
||||
|
||||
/* VMX_BASIC bits and bitmasks */
|
||||
#define VMX_BASIC_VMCS_SIZE_SHIFT 32
|
||||
#define VMX_BASIC_TRUE_CTLS (1ULL << 55)
|
||||
#define VMX_BASIC_64 0x0001000000000000LLU
|
||||
#define VMX_BASIC_MEM_TYPE_SHIFT 50
|
||||
#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
|
||||
#define VMX_BASIC_MEM_TYPE_WB 6LLU
|
||||
#define VMX_BASIC_INOUT 0x0040000000000000LLU
|
||||
|
||||
/* MSR_IA32_VMX_MISC bits */
|
||||
#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
|
||||
#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
|
||||
/* AMD-V MSRs */
|
||||
|
||||
#define MSR_VM_CR 0xc0010114
|
||||
#define MSR_VM_IGNNE 0xc0010115
|
||||
#define MSR_VM_HSAVE_PA 0xc0010117
|
||||
|
||||
#endif /* _ASM_X86_MSR_INDEX_H */
|
||||
@ -0,0 +1,13 @@
|
||||
#ifndef _ASM_X86_MSR_H
|
||||
#define _ASM_X86_MSR_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
#define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8])
|
||||
#define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8])
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* _ASM_X86_MSR_H */
|
||||
@ -0,0 +1,123 @@
|
||||
/* Generic MTRR (Memory Type Range Register) ioctls.
|
||||
|
||||
Copyright (C) 1997-1999 Richard Gooch
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Library General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Library General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Library General Public
|
||||
License along with this library; if not, write to the Free
|
||||
Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
|
||||
Richard Gooch may be reached by email at rgooch@atnf.csiro.au
|
||||
The postal address is:
|
||||
Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
|
||||
*/
|
||||
#ifndef _ASM_X86_MTRR_H
|
||||
#define _ASM_X86_MTRR_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <linux/errno.h>
|
||||
|
||||
#define MTRR_IOCTL_BASE 'M'
|
||||
|
||||
/* Warning: this structure has a different order from i386
|
||||
on x86-64. The 32bit emulation code takes care of that.
|
||||
But you need to use this for 64bit, otherwise your X server
|
||||
will break. */
|
||||
|
||||
#ifdef __i386__
|
||||
struct mtrr_sentry {
|
||||
unsigned long base; /* Base address */
|
||||
unsigned int size; /* Size of region */
|
||||
unsigned int type; /* Type of region */
|
||||
};
|
||||
|
||||
struct mtrr_gentry {
|
||||
unsigned int regnum; /* Register number */
|
||||
unsigned long base; /* Base address */
|
||||
unsigned int size; /* Size of region */
|
||||
unsigned int type; /* Type of region */
|
||||
};
|
||||
|
||||
#else /* __i386__ */
|
||||
|
||||
struct mtrr_sentry {
|
||||
__u64 base; /* Base address */
|
||||
__u32 size; /* Size of region */
|
||||
__u32 type; /* Type of region */
|
||||
};
|
||||
|
||||
struct mtrr_gentry {
|
||||
__u64 base; /* Base address */
|
||||
__u32 size; /* Size of region */
|
||||
__u32 regnum; /* Register number */
|
||||
__u32 type; /* Type of region */
|
||||
__u32 _pad; /* Unused */
|
||||
};
|
||||
|
||||
#endif /* !__i386__ */
|
||||
|
||||
struct mtrr_var_range {
|
||||
__u32 base_lo;
|
||||
__u32 base_hi;
|
||||
__u32 mask_lo;
|
||||
__u32 mask_hi;
|
||||
};
|
||||
|
||||
/* In the Intel processor's MTRR interface, the MTRR type is always held in
|
||||
an 8 bit field: */
|
||||
typedef __u8 mtrr_type;
|
||||
|
||||
#define MTRR_NUM_FIXED_RANGES 88
|
||||
#define MTRR_MAX_VAR_RANGES 256
|
||||
|
||||
struct mtrr_state_type {
|
||||
struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES];
|
||||
mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES];
|
||||
unsigned char enabled;
|
||||
unsigned char have_fixed;
|
||||
mtrr_type def_type;
|
||||
};
|
||||
|
||||
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
|
||||
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
||||
|
||||
/* These are the various ioctls */
|
||||
#define MTRRIOC_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry)
|
||||
#define MTRRIOC_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry)
|
||||
#define MTRRIOC_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct mtrr_sentry)
|
||||
#define MTRRIOC_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry)
|
||||
#define MTRRIOC_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct mtrr_sentry)
|
||||
#define MTRRIOC_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct mtrr_sentry)
|
||||
#define MTRRIOC_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct mtrr_sentry)
|
||||
#define MTRRIOC_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct mtrr_sentry)
|
||||
#define MTRRIOC_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry)
|
||||
#define MTRRIOC_KILL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 9, struct mtrr_sentry)
|
||||
|
||||
/* MTRR memory types, which are defined in SDM */
|
||||
#define MTRR_TYPE_UNCACHABLE 0
|
||||
#define MTRR_TYPE_WRCOMB 1
|
||||
/*#define MTRR_TYPE_ 2*/
|
||||
/*#define MTRR_TYPE_ 3*/
|
||||
#define MTRR_TYPE_WRTHROUGH 4
|
||||
#define MTRR_TYPE_WRPROT 5
|
||||
#define MTRR_TYPE_WRBACK 6
|
||||
#define MTRR_NUM_TYPES 7
|
||||
|
||||
/*
|
||||
* Invalid MTRR memory type. mtrr_type_lookup() returns this value when
|
||||
* MTRRs are disabled. Note, this value is allocated from the reserved
|
||||
* values (0x7-0xff) of the MTRR memory types.
|
||||
*/
|
||||
#define MTRR_TYPE_INVALID 0xff
|
||||
|
||||
#endif /* _ASM_X86_MTRR_H */
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/param.h>
|
||||
@ -0,0 +1,33 @@
|
||||
#ifndef _ASM_X86_PERF_REGS_H
|
||||
#define _ASM_X86_PERF_REGS_H
|
||||
|
||||
enum perf_event_x86_regs {
|
||||
PERF_REG_X86_AX,
|
||||
PERF_REG_X86_BX,
|
||||
PERF_REG_X86_CX,
|
||||
PERF_REG_X86_DX,
|
||||
PERF_REG_X86_SI,
|
||||
PERF_REG_X86_DI,
|
||||
PERF_REG_X86_BP,
|
||||
PERF_REG_X86_SP,
|
||||
PERF_REG_X86_IP,
|
||||
PERF_REG_X86_FLAGS,
|
||||
PERF_REG_X86_CS,
|
||||
PERF_REG_X86_SS,
|
||||
PERF_REG_X86_DS,
|
||||
PERF_REG_X86_ES,
|
||||
PERF_REG_X86_FS,
|
||||
PERF_REG_X86_GS,
|
||||
PERF_REG_X86_R8,
|
||||
PERF_REG_X86_R9,
|
||||
PERF_REG_X86_R10,
|
||||
PERF_REG_X86_R11,
|
||||
PERF_REG_X86_R12,
|
||||
PERF_REG_X86_R13,
|
||||
PERF_REG_X86_R14,
|
||||
PERF_REG_X86_R15,
|
||||
|
||||
PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
|
||||
PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
|
||||
};
|
||||
#endif /* _ASM_X86_PERF_REGS_H */
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/poll.h>
|
||||
@ -0,0 +1,7 @@
|
||||
# ifdef __i386__
|
||||
# include <asm/posix_types_32.h>
|
||||
# elif defined(__ILP32__)
|
||||
# include <asm/posix_types_x32.h>
|
||||
# else
|
||||
# include <asm/posix_types_64.h>
|
||||
# endif
|
||||
@ -0,0 +1,25 @@
|
||||
#ifndef _ASM_X86_POSIX_TYPES_32_H
|
||||
#define _ASM_X86_POSIX_TYPES_32_H
|
||||
|
||||
/*
|
||||
* This file is generally used by user-level software, so you need to
|
||||
* be a little careful about namespace pollution etc. Also, we cannot
|
||||
* assume GCC is being used.
|
||||
*/
|
||||
|
||||
typedef unsigned short __kernel_mode_t;
|
||||
#define __kernel_mode_t __kernel_mode_t
|
||||
|
||||
typedef unsigned short __kernel_ipc_pid_t;
|
||||
#define __kernel_ipc_pid_t __kernel_ipc_pid_t
|
||||
|
||||
typedef unsigned short __kernel_uid_t;
|
||||
typedef unsigned short __kernel_gid_t;
|
||||
#define __kernel_uid_t __kernel_uid_t
|
||||
|
||||
typedef unsigned short __kernel_old_dev_t;
|
||||
#define __kernel_old_dev_t __kernel_old_dev_t
|
||||
|
||||
#include <asm-generic/posix_types.h>
|
||||
|
||||
#endif /* _ASM_X86_POSIX_TYPES_32_H */
|
||||
@ -0,0 +1,19 @@
|
||||
#ifndef _ASM_X86_POSIX_TYPES_64_H
|
||||
#define _ASM_X86_POSIX_TYPES_64_H
|
||||
|
||||
/*
|
||||
* This file is generally used by user-level software, so you need to
|
||||
* be a little careful about namespace pollution etc. Also, we cannot
|
||||
* assume GCC is being used.
|
||||
*/
|
||||
|
||||
typedef unsigned short __kernel_old_uid_t;
|
||||
typedef unsigned short __kernel_old_gid_t;
|
||||
#define __kernel_old_uid_t __kernel_old_uid_t
|
||||
|
||||
typedef unsigned long __kernel_old_dev_t;
|
||||
#define __kernel_old_dev_t __kernel_old_dev_t
|
||||
|
||||
#include <asm-generic/posix_types.h>
|
||||
|
||||
#endif /* _ASM_X86_POSIX_TYPES_64_H */
|
||||
@ -0,0 +1,19 @@
|
||||
#ifndef _ASM_X86_POSIX_TYPES_X32_H
|
||||
#define _ASM_X86_POSIX_TYPES_X32_H
|
||||
|
||||
/*
|
||||
* This file is only used by user-level software, so you need to
|
||||
* be a little careful about namespace pollution etc. Also, we cannot
|
||||
* assume GCC is being used.
|
||||
*
|
||||
* These types should generally match the ones used by the 64-bit kernel,
|
||||
*
|
||||
*/
|
||||
|
||||
typedef long long __kernel_long_t;
|
||||
typedef unsigned long long __kernel_ulong_t;
|
||||
#define __kernel_long_t __kernel_long_t
|
||||
|
||||
#include <asm/posix_types_64.h>
|
||||
|
||||
#endif /* _ASM_X86_POSIX_TYPES_X32_H */
|
||||
@ -0,0 +1,9 @@
|
||||
#ifndef _ASM_X86_PRCTL_H
|
||||
#define _ASM_X86_PRCTL_H
|
||||
|
||||
#define ARCH_SET_GS 0x1001
|
||||
#define ARCH_SET_FS 0x1002
|
||||
#define ARCH_GET_FS 0x1003
|
||||
#define ARCH_GET_GS 0x1004
|
||||
|
||||
#endif /* _ASM_X86_PRCTL_H */
|
||||
@ -0,0 +1,151 @@
|
||||
#ifndef _ASM_X86_PROCESSOR_FLAGS_H
|
||||
#define _ASM_X86_PROCESSOR_FLAGS_H
|
||||
/* Various flags defined: can be included from assembler. */
|
||||
|
||||
#include <linux/const.h>
|
||||
|
||||
/*
|
||||
* EFLAGS bits
|
||||
*/
|
||||
#define X86_EFLAGS_CF_BIT 0 /* Carry Flag */
|
||||
#define X86_EFLAGS_CF _BITUL(X86_EFLAGS_CF_BIT)
|
||||
#define X86_EFLAGS_FIXED_BIT 1 /* Bit 1 - always on */
|
||||
#define X86_EFLAGS_FIXED _BITUL(X86_EFLAGS_FIXED_BIT)
|
||||
#define X86_EFLAGS_PF_BIT 2 /* Parity Flag */
|
||||
#define X86_EFLAGS_PF _BITUL(X86_EFLAGS_PF_BIT)
|
||||
#define X86_EFLAGS_AF_BIT 4 /* Auxiliary carry Flag */
|
||||
#define X86_EFLAGS_AF _BITUL(X86_EFLAGS_AF_BIT)
|
||||
#define X86_EFLAGS_ZF_BIT 6 /* Zero Flag */
|
||||
#define X86_EFLAGS_ZF _BITUL(X86_EFLAGS_ZF_BIT)
|
||||
#define X86_EFLAGS_SF_BIT 7 /* Sign Flag */
|
||||
#define X86_EFLAGS_SF _BITUL(X86_EFLAGS_SF_BIT)
|
||||
#define X86_EFLAGS_TF_BIT 8 /* Trap Flag */
|
||||
#define X86_EFLAGS_TF _BITUL(X86_EFLAGS_TF_BIT)
|
||||
#define X86_EFLAGS_IF_BIT 9 /* Interrupt Flag */
|
||||
#define X86_EFLAGS_IF _BITUL(X86_EFLAGS_IF_BIT)
|
||||
#define X86_EFLAGS_DF_BIT 10 /* Direction Flag */
|
||||
#define X86_EFLAGS_DF _BITUL(X86_EFLAGS_DF_BIT)
|
||||
#define X86_EFLAGS_OF_BIT 11 /* Overflow Flag */
|
||||
#define X86_EFLAGS_OF _BITUL(X86_EFLAGS_OF_BIT)
|
||||
#define X86_EFLAGS_IOPL_BIT 12 /* I/O Privilege Level (2 bits) */
|
||||
#define X86_EFLAGS_IOPL (_AC(3,UL) << X86_EFLAGS_IOPL_BIT)
|
||||
#define X86_EFLAGS_NT_BIT 14 /* Nested Task */
|
||||
#define X86_EFLAGS_NT _BITUL(X86_EFLAGS_NT_BIT)
|
||||
#define X86_EFLAGS_RF_BIT 16 /* Resume Flag */
|
||||
#define X86_EFLAGS_RF _BITUL(X86_EFLAGS_RF_BIT)
|
||||
#define X86_EFLAGS_VM_BIT 17 /* Virtual Mode */
|
||||
#define X86_EFLAGS_VM _BITUL(X86_EFLAGS_VM_BIT)
|
||||
#define X86_EFLAGS_AC_BIT 18 /* Alignment Check/Access Control */
|
||||
#define X86_EFLAGS_AC _BITUL(X86_EFLAGS_AC_BIT)
|
||||
#define X86_EFLAGS_VIF_BIT 19 /* Virtual Interrupt Flag */
|
||||
#define X86_EFLAGS_VIF _BITUL(X86_EFLAGS_VIF_BIT)
|
||||
#define X86_EFLAGS_VIP_BIT 20 /* Virtual Interrupt Pending */
|
||||
#define X86_EFLAGS_VIP _BITUL(X86_EFLAGS_VIP_BIT)
|
||||
#define X86_EFLAGS_ID_BIT 21 /* CPUID detection */
|
||||
#define X86_EFLAGS_ID _BITUL(X86_EFLAGS_ID_BIT)
|
||||
|
||||
/*
|
||||
* Basic CPU control in CR0
|
||||
*/
|
||||
#define X86_CR0_PE_BIT 0 /* Protection Enable */
|
||||
#define X86_CR0_PE _BITUL(X86_CR0_PE_BIT)
|
||||
#define X86_CR0_MP_BIT 1 /* Monitor Coprocessor */
|
||||
#define X86_CR0_MP _BITUL(X86_CR0_MP_BIT)
|
||||
#define X86_CR0_EM_BIT 2 /* Emulation */
|
||||
#define X86_CR0_EM _BITUL(X86_CR0_EM_BIT)
|
||||
#define X86_CR0_TS_BIT 3 /* Task Switched */
|
||||
#define X86_CR0_TS _BITUL(X86_CR0_TS_BIT)
|
||||
#define X86_CR0_ET_BIT 4 /* Extension Type */
|
||||
#define X86_CR0_ET _BITUL(X86_CR0_ET_BIT)
|
||||
#define X86_CR0_NE_BIT 5 /* Numeric Error */
|
||||
#define X86_CR0_NE _BITUL(X86_CR0_NE_BIT)
|
||||
#define X86_CR0_WP_BIT 16 /* Write Protect */
|
||||
#define X86_CR0_WP _BITUL(X86_CR0_WP_BIT)
|
||||
#define X86_CR0_AM_BIT 18 /* Alignment Mask */
|
||||
#define X86_CR0_AM _BITUL(X86_CR0_AM_BIT)
|
||||
#define X86_CR0_NW_BIT 29 /* Not Write-through */
|
||||
#define X86_CR0_NW _BITUL(X86_CR0_NW_BIT)
|
||||
#define X86_CR0_CD_BIT 30 /* Cache Disable */
|
||||
#define X86_CR0_CD _BITUL(X86_CR0_CD_BIT)
|
||||
#define X86_CR0_PG_BIT 31 /* Paging */
|
||||
#define X86_CR0_PG _BITUL(X86_CR0_PG_BIT)
|
||||
|
||||
/*
|
||||
* Paging options in CR3
|
||||
*/
|
||||
#define X86_CR3_PWT_BIT 3 /* Page Write Through */
|
||||
#define X86_CR3_PWT _BITUL(X86_CR3_PWT_BIT)
|
||||
#define X86_CR3_PCD_BIT 4 /* Page Cache Disable */
|
||||
#define X86_CR3_PCD _BITUL(X86_CR3_PCD_BIT)
|
||||
#define X86_CR3_PCID_MASK _AC(0x00000fff,UL) /* PCID Mask */
|
||||
|
||||
/*
|
||||
* Intel CPU features in CR4
|
||||
*/
|
||||
#define X86_CR4_VME_BIT 0 /* enable vm86 extensions */
|
||||
#define X86_CR4_VME _BITUL(X86_CR4_VME_BIT)
|
||||
#define X86_CR4_PVI_BIT 1 /* virtual interrupts flag enable */
|
||||
#define X86_CR4_PVI _BITUL(X86_CR4_PVI_BIT)
|
||||
#define X86_CR4_TSD_BIT 2 /* disable time stamp at ipl 3 */
|
||||
#define X86_CR4_TSD _BITUL(X86_CR4_TSD_BIT)
|
||||
#define X86_CR4_DE_BIT 3 /* enable debugging extensions */
|
||||
#define X86_CR4_DE _BITUL(X86_CR4_DE_BIT)
|
||||
#define X86_CR4_PSE_BIT 4 /* enable page size extensions */
|
||||
#define X86_CR4_PSE _BITUL(X86_CR4_PSE_BIT)
|
||||
#define X86_CR4_PAE_BIT 5 /* enable physical address extensions */
|
||||
#define X86_CR4_PAE _BITUL(X86_CR4_PAE_BIT)
|
||||
#define X86_CR4_MCE_BIT 6 /* Machine check enable */
|
||||
#define X86_CR4_MCE _BITUL(X86_CR4_MCE_BIT)
|
||||
#define X86_CR4_PGE_BIT 7 /* enable global pages */
|
||||
#define X86_CR4_PGE _BITUL(X86_CR4_PGE_BIT)
|
||||
#define X86_CR4_PCE_BIT 8 /* enable performance counters at ipl 3 */
|
||||
#define X86_CR4_PCE _BITUL(X86_CR4_PCE_BIT)
|
||||
#define X86_CR4_OSFXSR_BIT 9 /* enable fast FPU save and restore */
|
||||
#define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT)
|
||||
#define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */
|
||||
#define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT)
|
||||
#define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */
|
||||
#define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT)
|
||||
#define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */
|
||||
#define X86_CR4_SMXE _BITUL(X86_CR4_SMXE_BIT)
|
||||
#define X86_CR4_FSGSBASE_BIT 16 /* enable RDWRFSGS support */
|
||||
#define X86_CR4_FSGSBASE _BITUL(X86_CR4_FSGSBASE_BIT)
|
||||
#define X86_CR4_PCIDE_BIT 17 /* enable PCID support */
|
||||
#define X86_CR4_PCIDE _BITUL(X86_CR4_PCIDE_BIT)
|
||||
#define X86_CR4_OSXSAVE_BIT 18 /* enable xsave and xrestore */
|
||||
#define X86_CR4_OSXSAVE _BITUL(X86_CR4_OSXSAVE_BIT)
|
||||
#define X86_CR4_SMEP_BIT 20 /* enable SMEP support */
|
||||
#define X86_CR4_SMEP _BITUL(X86_CR4_SMEP_BIT)
|
||||
#define X86_CR4_SMAP_BIT 21 /* enable SMAP support */
|
||||
#define X86_CR4_SMAP _BITUL(X86_CR4_SMAP_BIT)
|
||||
|
||||
/*
|
||||
* x86-64 Task Priority Register, CR8
|
||||
*/
|
||||
#define X86_CR8_TPR _AC(0x0000000f,UL) /* task priority register */
|
||||
|
||||
/*
|
||||
* AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
|
||||
*/
|
||||
|
||||
/*
|
||||
* NSC/Cyrix CPU configuration register indexes
|
||||
*/
|
||||
#define CX86_PCR0 0x20
|
||||
#define CX86_GCR 0xb8
|
||||
#define CX86_CCR0 0xc0
|
||||
#define CX86_CCR1 0xc1
|
||||
#define CX86_CCR2 0xc2
|
||||
#define CX86_CCR3 0xc3
|
||||
#define CX86_CCR4 0xe8
|
||||
#define CX86_CCR5 0xe9
|
||||
#define CX86_CCR6 0xea
|
||||
#define CX86_CCR7 0xeb
|
||||
#define CX86_PCR1 0xf0
|
||||
#define CX86_DIR0 0xfe
|
||||
#define CX86_DIR1 0xff
|
||||
#define CX86_ARR_BASE 0xc4
|
||||
#define CX86_RCR_BASE 0xdc
|
||||
|
||||
|
||||
#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
|
||||
@ -0,0 +1,93 @@
|
||||
#ifndef _ASM_X86_PTRACE_ABI_H
|
||||
#define _ASM_X86_PTRACE_ABI_H
|
||||
|
||||
#ifdef __i386__
|
||||
|
||||
#define EBX 0
|
||||
#define ECX 1
|
||||
#define EDX 2
|
||||
#define ESI 3
|
||||
#define EDI 4
|
||||
#define EBP 5
|
||||
#define EAX 6
|
||||
#define DS 7
|
||||
#define ES 8
|
||||
#define FS 9
|
||||
#define GS 10
|
||||
#define ORIG_EAX 11
|
||||
#define EIP 12
|
||||
#define CS 13
|
||||
#define EFL 14
|
||||
#define UESP 15
|
||||
#define SS 16
|
||||
#define FRAME_SIZE 17
|
||||
|
||||
#else /* __i386__ */
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__FRAME_OFFSETS)
|
||||
/*
|
||||
* C ABI says these regs are callee-preserved. They aren't saved on kernel entry
|
||||
* unless syscall needs a complete, fully filled "struct pt_regs".
|
||||
*/
|
||||
#define R15 0
|
||||
#define R14 8
|
||||
#define R13 16
|
||||
#define R12 24
|
||||
#define RBP 32
|
||||
#define RBX 40
|
||||
/* These regs are callee-clobbered. Always saved on kernel entry. */
|
||||
#define R11 48
|
||||
#define R10 56
|
||||
#define R9 64
|
||||
#define R8 72
|
||||
#define RAX 80
|
||||
#define RCX 88
|
||||
#define RDX 96
|
||||
#define RSI 104
|
||||
#define RDI 112
|
||||
/*
|
||||
* On syscall entry, this is syscall#. On CPU exception, this is error code.
|
||||
* On hw interrupt, it's IRQ number:
|
||||
*/
|
||||
#define ORIG_RAX 120
|
||||
/* Return frame for iretq */
|
||||
#define RIP 128
|
||||
#define CS 136
|
||||
#define EFLAGS 144
|
||||
#define RSP 152
|
||||
#define SS 160
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* top of stack page */
|
||||
#define FRAME_SIZE 168
|
||||
|
||||
#endif /* !__i386__ */
|
||||
|
||||
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
|
||||
#define PTRACE_GETREGS 12
|
||||
#define PTRACE_SETREGS 13
|
||||
#define PTRACE_GETFPREGS 14
|
||||
#define PTRACE_SETFPREGS 15
|
||||
#define PTRACE_GETFPXREGS 18
|
||||
#define PTRACE_SETFPXREGS 19
|
||||
|
||||
#define PTRACE_OLDSETOPTIONS 21
|
||||
|
||||
/* only useful for access 32bit programs / kernels */
|
||||
#define PTRACE_GET_THREAD_AREA 25
|
||||
#define PTRACE_SET_THREAD_AREA 26
|
||||
|
||||
#ifdef __x86_64__
|
||||
# define PTRACE_ARCH_PRCTL 30
|
||||
#endif
|
||||
|
||||
#define PTRACE_SYSEMU 31
|
||||
#define PTRACE_SYSEMU_SINGLESTEP 32
|
||||
|
||||
#define PTRACE_SINGLEBLOCK 33 /* resume execution until next branch */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/types.h>
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_X86_PTRACE_ABI_H */
|
||||
@ -0,0 +1,81 @@
|
||||
#ifndef _ASM_X86_PTRACE_H
|
||||
#define _ASM_X86_PTRACE_H
|
||||
|
||||
/* For */
|
||||
#include <asm/ptrace-abi.h>
|
||||
#include <asm/processor-flags.h>
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef __i386__
|
||||
/* this struct defines the way the registers are stored on the
|
||||
stack during a system call. */
|
||||
|
||||
|
||||
struct pt_regs {
|
||||
long ebx;
|
||||
long ecx;
|
||||
long edx;
|
||||
long esi;
|
||||
long edi;
|
||||
long ebp;
|
||||
long eax;
|
||||
int xds;
|
||||
int xes;
|
||||
int xfs;
|
||||
int xgs;
|
||||
long orig_eax;
|
||||
long eip;
|
||||
int xcs;
|
||||
long eflags;
|
||||
long esp;
|
||||
int xss;
|
||||
};
|
||||
|
||||
|
||||
#else /* __i386__ */
|
||||
|
||||
|
||||
struct pt_regs {
|
||||
/*
|
||||
* C ABI says these regs are callee-preserved. They aren't saved on kernel entry
|
||||
* unless syscall needs a complete, fully filled "struct pt_regs".
|
||||
*/
|
||||
unsigned long r15;
|
||||
unsigned long r14;
|
||||
unsigned long r13;
|
||||
unsigned long r12;
|
||||
unsigned long rbp;
|
||||
unsigned long rbx;
|
||||
/* These regs are callee-clobbered. Always saved on kernel entry. */
|
||||
unsigned long r11;
|
||||
unsigned long r10;
|
||||
unsigned long r9;
|
||||
unsigned long r8;
|
||||
unsigned long rax;
|
||||
unsigned long rcx;
|
||||
unsigned long rdx;
|
||||
unsigned long rsi;
|
||||
unsigned long rdi;
|
||||
/*
|
||||
* On syscall entry, this is syscall#. On CPU exception, this is error code.
|
||||
* On hw interrupt, it's IRQ number:
|
||||
*/
|
||||
unsigned long orig_rax;
|
||||
/* Return frame for iretq */
|
||||
unsigned long rip;
|
||||
unsigned long cs;
|
||||
unsigned long eflags;
|
||||
unsigned long rsp;
|
||||
unsigned long ss;
|
||||
/* top of stack page */
|
||||
};
|
||||
|
||||
#endif /* !__i386__ */
|
||||
|
||||
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_X86_PTRACE_H */
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/resource.h>
|
||||
@ -0,0 +1,24 @@
|
||||
#ifndef _ASM_X86_SEMBUF_H
|
||||
#define _ASM_X86_SEMBUF_H
|
||||
|
||||
/*
|
||||
* The semid64_ds structure for x86 architecture.
|
||||
* Note extra padding because this structure is passed back and forth
|
||||
* between kernel and user space.
|
||||
*
|
||||
* Pad space is left for:
|
||||
* - 64-bit time_t to solve y2038 problem
|
||||
* - 2 miscellaneous 32-bit values
|
||||
*/
|
||||
struct semid64_ds {
|
||||
struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
|
||||
__kernel_time_t sem_otime; /* last semop time */
|
||||
__kernel_ulong_t __unused1;
|
||||
__kernel_time_t sem_ctime; /* last change time */
|
||||
__kernel_ulong_t __unused2;
|
||||
__kernel_ulong_t sem_nsems; /* no. of semaphores in array */
|
||||
__kernel_ulong_t __unused3;
|
||||
__kernel_ulong_t __unused4;
|
||||
};
|
||||
|
||||
#endif /* _ASM_X86_SEMBUF_H */
|
||||
@ -0,0 +1 @@
|
||||
/* */
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/shmbuf.h>
|
||||
@ -0,0 +1,351 @@
|
||||
#ifndef _ASM_X86_SIGCONTEXT_H
|
||||
#define _ASM_X86_SIGCONTEXT_H
|
||||
|
||||
/*
|
||||
* Linux signal context definitions. The sigcontext includes a complex
|
||||
* hierarchy of CPU and FPU state, available to user-space (on the stack) when
|
||||
* a signal handler is executed.
|
||||
*
|
||||
* As over the years this ABI grew from its very simple roots towards
|
||||
* supporting more and more CPU state organically, some of the details (which
|
||||
* were rather clever hacks back in the days) became a bit quirky by today.
|
||||
*
|
||||
* The current ABI includes flexible provisions for future extensions, so we
|
||||
* won't have to grow new quirks for quite some time. Promise!
|
||||
*/
|
||||
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define FP_XSTATE_MAGIC1 0x46505853U
|
||||
#define FP_XSTATE_MAGIC2 0x46505845U
|
||||
#define FP_XSTATE_MAGIC2_SIZE sizeof(FP_XSTATE_MAGIC2)
|
||||
|
||||
/*
|
||||
* Bytes 464..511 in the current 512-byte layout of the FXSAVE/FXRSTOR frame
|
||||
* are reserved for SW usage. On CPUs supporting XSAVE/XRSTOR, these bytes are
|
||||
* used to extend the fpstate pointer in the sigcontext, which now includes the
|
||||
* extended state information along with fpstate information.
|
||||
*
|
||||
* If sw_reserved.magic1 == FP_XSTATE_MAGIC1 then there's a
|
||||
* sw_reserved.extended_size bytes large extended context area present. (The
|
||||
* last 32-bit word of this extended area (at the
|
||||
* fpstate+extended_size-FP_XSTATE_MAGIC2_SIZE address) is set to
|
||||
* FP_XSTATE_MAGIC2 so that you can sanity check your size calculations.)
|
||||
*
|
||||
* This extended area typically grows with newer CPUs that have larger and
|
||||
* larger XSAVE areas.
|
||||
*/
|
||||
struct _fpx_sw_bytes {
|
||||
/*
|
||||
* If set to FP_XSTATE_MAGIC1 then this is an xstate context.
|
||||
* 0 if a legacy frame.
|
||||
*/
|
||||
__u32 magic1;
|
||||
|
||||
/*
|
||||
* Total size of the fpstate area:
|
||||
*
|
||||
* - if magic1 == 0 then it's sizeof(struct _fpstate)
|
||||
* - if magic1 == FP_XSTATE_MAGIC1 then it's sizeof(struct _xstate)
|
||||
* plus extensions (if any)
|
||||
*/
|
||||
__u32 extended_size;
|
||||
|
||||
/*
|
||||
* Feature bit mask (including FP/SSE/extended state) that is present
|
||||
* in the memory layout:
|
||||
*/
|
||||
__u64 xfeatures;
|
||||
|
||||
/*
|
||||
* Actual XSAVE state size, based on the xfeatures saved in the layout.
|
||||
* 'extended_size' is greater than 'xstate_size':
|
||||
*/
|
||||
__u32 xstate_size;
|
||||
|
||||
/* For future use: */
|
||||
__u32 padding[7];
|
||||
};
|
||||
|
||||
/*
|
||||
* As documented in the iBCS2 standard:
|
||||
*
|
||||
* The first part of "struct _fpstate" is just the normal i387 hardware setup,
|
||||
* the extra "status" word is used to save the coprocessor status word before
|
||||
* entering the handler.
|
||||
*
|
||||
* The FPU state data structure has had to grow to accommodate the extended FPU
|
||||
* state required by the Streaming SIMD Extensions. There is no documented
|
||||
* standard to accomplish this at the moment.
|
||||
*/
|
||||
|
||||
/* 10-byte legacy floating point register: */
|
||||
struct _fpreg {
|
||||
__u16 significand[4];
|
||||
__u16 exponent;
|
||||
};
|
||||
|
||||
/* 16-byte floating point register: */
|
||||
struct _fpxreg {
|
||||
__u16 significand[4];
|
||||
__u16 exponent;
|
||||
__u16 padding[3];
|
||||
};
|
||||
|
||||
/* 16-byte XMM register: */
|
||||
struct _xmmreg {
|
||||
__u32 element[4];
|
||||
};
|
||||
|
||||
#define X86_FXSR_MAGIC 0x0000
|
||||
|
||||
/*
|
||||
* The 32-bit FPU frame:
|
||||
*/
|
||||
struct _fpstate_32 {
|
||||
/* Legacy FPU environment: */
|
||||
__u32 cw;
|
||||
__u32 sw;
|
||||
__u32 tag;
|
||||
__u32 ipoff;
|
||||
__u32 cssel;
|
||||
__u32 dataoff;
|
||||
__u32 datasel;
|
||||
struct _fpreg _st[8];
|
||||
__u16 status;
|
||||
__u16 magic; /* 0xffff: regular FPU data only */
|
||||
/* 0x0000: FXSR FPU data */
|
||||
|
||||
/* FXSR FPU environment */
|
||||
__u32 _fxsr_env[6]; /* FXSR FPU env is ignored */
|
||||
__u32 mxcsr;
|
||||
__u32 reserved;
|
||||
struct _fpxreg _fxsr_st[8]; /* FXSR FPU reg data is ignored */
|
||||
struct _xmmreg _xmm[8]; /* First 8 XMM registers */
|
||||
union {
|
||||
__u32 padding1[44]; /* Second 8 XMM registers plus padding */
|
||||
__u32 padding[44]; /* Alias name for old user-space */
|
||||
};
|
||||
|
||||
union {
|
||||
__u32 padding2[12];
|
||||
struct _fpx_sw_bytes sw_reserved; /* Potential extended state is encoded here */
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The 64-bit FPU frame. (FXSAVE format and later)
|
||||
*
|
||||
* Note1: If sw_reserved.magic1 == FP_XSTATE_MAGIC1 then the structure is
|
||||
* larger: 'struct _xstate'. Note that 'struct _xstate' embedds
|
||||
* 'struct _fpstate' so that you can always assume the _fpstate portion
|
||||
* exists so that you can check the magic value.
|
||||
*
|
||||
* Note2: Reserved fields may someday contain valuable data. Always
|
||||
* save/restore them when you change signal frames.
|
||||
*/
|
||||
struct _fpstate_64 {
|
||||
__u16 cwd;
|
||||
__u16 swd;
|
||||
/* Note this is not the same as the 32-bit/x87/FSAVE twd: */
|
||||
__u16 twd;
|
||||
__u16 fop;
|
||||
__u64 rip;
|
||||
__u64 rdp;
|
||||
__u32 mxcsr;
|
||||
__u32 mxcsr_mask;
|
||||
__u32 st_space[32]; /* 8x FP registers, 16 bytes each */
|
||||
__u32 xmm_space[64]; /* 16x XMM registers, 16 bytes each */
|
||||
__u32 reserved2[12];
|
||||
union {
|
||||
__u32 reserved3[12];
|
||||
struct _fpx_sw_bytes sw_reserved; /* Potential extended state is encoded here */
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef __i386__
|
||||
# define _fpstate _fpstate_32
|
||||
#else
|
||||
# define _fpstate _fpstate_64
|
||||
#endif
|
||||
|
||||
struct _header {
|
||||
__u64 xfeatures;
|
||||
__u64 reserved1[2];
|
||||
__u64 reserved2[5];
|
||||
};
|
||||
|
||||
struct _ymmh_state {
|
||||
/* 16x YMM registers, 16 bytes each: */
|
||||
__u32 ymmh_space[64];
|
||||
};
|
||||
|
||||
/*
|
||||
* Extended state pointed to by sigcontext::fpstate.
|
||||
*
|
||||
* In addition to the fpstate, information encoded in _xstate::xstate_hdr
|
||||
* indicates the presence of other extended state information supported
|
||||
* by the CPU and kernel:
|
||||
*/
|
||||
struct _xstate {
|
||||
struct _fpstate fpstate;
|
||||
struct _header xstate_hdr;
|
||||
struct _ymmh_state ymmh;
|
||||
/* New processor state extensions go here: */
|
||||
};
|
||||
|
||||
/*
|
||||
* The 32-bit signal frame:
|
||||
*/
|
||||
struct sigcontext_32 {
|
||||
__u16 gs, __gsh;
|
||||
__u16 fs, __fsh;
|
||||
__u16 es, __esh;
|
||||
__u16 ds, __dsh;
|
||||
__u32 di;
|
||||
__u32 si;
|
||||
__u32 bp;
|
||||
__u32 sp;
|
||||
__u32 bx;
|
||||
__u32 dx;
|
||||
__u32 cx;
|
||||
__u32 ax;
|
||||
__u32 trapno;
|
||||
__u32 err;
|
||||
__u32 ip;
|
||||
__u16 cs, __csh;
|
||||
__u32 flags;
|
||||
__u32 sp_at_signal;
|
||||
__u16 ss, __ssh;
|
||||
|
||||
/*
|
||||
* fpstate is really (struct _fpstate *) or (struct _xstate *)
|
||||
* depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved
|
||||
* bytes of (struct _fpstate) and FP_XSTATE_MAGIC2 present at the end
|
||||
* of extended memory layout. See comments at the definition of
|
||||
* (struct _fpx_sw_bytes)
|
||||
*/
|
||||
__u32 fpstate; /* Zero when no FPU/extended context */
|
||||
__u32 oldmask;
|
||||
__u32 cr2;
|
||||
};
|
||||
|
||||
/*
|
||||
* The 64-bit signal frame:
|
||||
*/
|
||||
struct sigcontext_64 {
|
||||
__u64 r8;
|
||||
__u64 r9;
|
||||
__u64 r10;
|
||||
__u64 r11;
|
||||
__u64 r12;
|
||||
__u64 r13;
|
||||
__u64 r14;
|
||||
__u64 r15;
|
||||
__u64 di;
|
||||
__u64 si;
|
||||
__u64 bp;
|
||||
__u64 bx;
|
||||
__u64 dx;
|
||||
__u64 ax;
|
||||
__u64 cx;
|
||||
__u64 sp;
|
||||
__u64 ip;
|
||||
__u64 flags;
|
||||
__u16 cs;
|
||||
__u16 gs;
|
||||
__u16 fs;
|
||||
__u16 __pad0;
|
||||
__u64 err;
|
||||
__u64 trapno;
|
||||
__u64 oldmask;
|
||||
__u64 cr2;
|
||||
|
||||
/*
|
||||
* fpstate is really (struct _fpstate *) or (struct _xstate *)
|
||||
* depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved
|
||||
* bytes of (struct _fpstate) and FP_XSTATE_MAGIC2 present at the end
|
||||
* of extended memory layout. See comments at the definition of
|
||||
* (struct _fpx_sw_bytes)
|
||||
*/
|
||||
__u64 fpstate; /* Zero when no FPU/extended context */
|
||||
__u64 reserved1[8];
|
||||
};
|
||||
|
||||
/*
|
||||
* Create the real 'struct sigcontext' type:
|
||||
*/
|
||||
|
||||
/*
|
||||
* The old user-space sigcontext definition, just in case user-space still
|
||||
* relies on it. The kernel definition (in asm/sigcontext.h) has unified
|
||||
* field names but otherwise the same layout.
|
||||
*/
|
||||
|
||||
#define _fpstate_ia32 _fpstate_32
|
||||
#define sigcontext_ia32 sigcontext_32
|
||||
|
||||
|
||||
# ifdef __i386__
|
||||
struct sigcontext {
|
||||
__u16 gs, __gsh;
|
||||
__u16 fs, __fsh;
|
||||
__u16 es, __esh;
|
||||
__u16 ds, __dsh;
|
||||
__u32 edi;
|
||||
__u32 esi;
|
||||
__u32 ebp;
|
||||
__u32 esp;
|
||||
__u32 ebx;
|
||||
__u32 edx;
|
||||
__u32 ecx;
|
||||
__u32 eax;
|
||||
__u32 trapno;
|
||||
__u32 err;
|
||||
__u32 eip;
|
||||
__u16 cs, __csh;
|
||||
__u32 eflags;
|
||||
__u32 esp_at_signal;
|
||||
__u16 ss, __ssh;
|
||||
struct _fpstate *fpstate;
|
||||
__u32 oldmask;
|
||||
__u32 cr2;
|
||||
};
|
||||
# else /* __x86_64__: */
|
||||
struct sigcontext {
|
||||
__u64 r8;
|
||||
__u64 r9;
|
||||
__u64 r10;
|
||||
__u64 r11;
|
||||
__u64 r12;
|
||||
__u64 r13;
|
||||
__u64 r14;
|
||||
__u64 r15;
|
||||
__u64 rdi;
|
||||
__u64 rsi;
|
||||
__u64 rbp;
|
||||
__u64 rbx;
|
||||
__u64 rdx;
|
||||
__u64 rax;
|
||||
__u64 rcx;
|
||||
__u64 rsp;
|
||||
__u64 rip;
|
||||
__u64 eflags; /* RFLAGS */
|
||||
__u16 cs;
|
||||
__u16 gs;
|
||||
__u16 fs;
|
||||
__u16 __pad0;
|
||||
__u64 err;
|
||||
__u64 trapno;
|
||||
__u64 oldmask;
|
||||
__u64 cr2;
|
||||
struct _fpstate *fpstate; /* Zero when no FPU context */
|
||||
# ifdef __ILP32__
|
||||
__u32 __fpstate_pad;
|
||||
# endif
|
||||
__u64 reserved1[8];
|
||||
};
|
||||
# endif /* __x86_64__ */
|
||||
|
||||
#endif /* _ASM_X86_SIGCONTEXT_H */
|
||||
@ -0,0 +1,8 @@
|
||||
#ifndef _ASM_X86_SIGCONTEXT32_H
|
||||
#define _ASM_X86_SIGCONTEXT32_H
|
||||
|
||||
/* This is a legacy file - all the type definitions are in sigcontext.h: */
|
||||
|
||||
#include <asm/sigcontext.h>
|
||||
|
||||
#endif /* _ASM_X86_SIGCONTEXT32_H */
|
||||
@ -0,0 +1,16 @@
|
||||
#ifndef _ASM_X86_SIGINFO_H
|
||||
#define _ASM_X86_SIGINFO_H
|
||||
|
||||
#ifdef __x86_64__
|
||||
# ifdef __ILP32__ /* x32 */
|
||||
typedef long long __kernel_si_clock_t __attribute__((aligned(4)));
|
||||
# define __ARCH_SI_CLOCK_T __kernel_si_clock_t
|
||||
# define __ARCH_SI_ATTRIBUTES __attribute__((aligned(8)))
|
||||
# else /* x86-64 */
|
||||
# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#include <asm-generic/siginfo.h>
|
||||
|
||||
#endif /* _ASM_X86_SIGINFO_H */
|
||||
@ -0,0 +1,131 @@
|
||||
#ifndef _ASM_X86_SIGNAL_H
|
||||
#define _ASM_X86_SIGNAL_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/types.h>
|
||||
#include <linux/time.h>
|
||||
|
||||
|
||||
/* Avoid too many header ordering problems. */
|
||||
struct siginfo;
|
||||
|
||||
/* Here we must cater to libcs that poke about in kernel headers. */
|
||||
|
||||
#define NSIG 32
|
||||
typedef unsigned long sigset_t;
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
||||
#define SIGHUP 1
|
||||
#define SIGINT 2
|
||||
#define SIGQUIT 3
|
||||
#define SIGILL 4
|
||||
#define SIGTRAP 5
|
||||
#define SIGABRT 6
|
||||
#define SIGIOT 6
|
||||
#define SIGBUS 7
|
||||
#define SIGFPE 8
|
||||
#define SIGKILL 9
|
||||
#define SIGUSR1 10
|
||||
#define SIGSEGV 11
|
||||
#define SIGUSR2 12
|
||||
#define SIGPIPE 13
|
||||
#define SIGALRM 14
|
||||
#define SIGTERM 15
|
||||
#define SIGSTKFLT 16
|
||||
#define SIGCHLD 17
|
||||
#define SIGCONT 18
|
||||
#define SIGSTOP 19
|
||||
#define SIGTSTP 20
|
||||
#define SIGTTIN 21
|
||||
#define SIGTTOU 22
|
||||
#define SIGURG 23
|
||||
#define SIGXCPU 24
|
||||
#define SIGXFSZ 25
|
||||
#define SIGVTALRM 26
|
||||
#define SIGPROF 27
|
||||
#define SIGWINCH 28
|
||||
#define SIGIO 29
|
||||
#define SIGPOLL SIGIO
|
||||
/*
|
||||
#define SIGLOST 29
|
||||
*/
|
||||
#define SIGPWR 30
|
||||
#define SIGSYS 31
|
||||
#define SIGUNUSED 31
|
||||
|
||||
/* These should not be considered constants from userland. */
|
||||
#define SIGRTMIN 32
|
||||
#define SIGRTMAX _NSIG
|
||||
|
||||
/*
|
||||
* SA_FLAGS values:
|
||||
*
|
||||
* SA_ONSTACK indicates that a registered stack_t will be used.
|
||||
* SA_RESTART flag to get restarting signals (which were the default long ago)
|
||||
* SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
|
||||
* SA_RESETHAND clears the handler when the signal is delivered.
|
||||
* SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
|
||||
* SA_NODEFER prevents the current signal from being masked in the handler.
|
||||
*
|
||||
* SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
|
||||
* Unix names RESETHAND and NODEFER respectively.
|
||||
*/
|
||||
#define SA_NOCLDSTOP 0x00000001u
|
||||
#define SA_NOCLDWAIT 0x00000002u
|
||||
#define SA_SIGINFO 0x00000004u
|
||||
#define SA_ONSTACK 0x08000000u
|
||||
#define SA_RESTART 0x10000000u
|
||||
#define SA_NODEFER 0x40000000u
|
||||
#define SA_RESETHAND 0x80000000u
|
||||
|
||||
#define SA_NOMASK SA_NODEFER
|
||||
#define SA_ONESHOT SA_RESETHAND
|
||||
|
||||
#define SA_RESTORER 0x04000000
|
||||
|
||||
#define MINSIGSTKSZ 2048
|
||||
#define SIGSTKSZ 8192
|
||||
|
||||
#include <asm-generic/signal-defs.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
||||
/* Here we must cater to libcs that poke about in kernel headers. */
|
||||
#ifdef __i386__
|
||||
|
||||
struct sigaction {
|
||||
union {
|
||||
__sighandler_t _sa_handler;
|
||||
void (*_sa_sigaction)(int, struct siginfo *, void *);
|
||||
} _u;
|
||||
sigset_t sa_mask;
|
||||
unsigned long sa_flags;
|
||||
void (*sa_restorer)(void);
|
||||
};
|
||||
|
||||
#define sa_handler _u._sa_handler
|
||||
#define sa_sigaction _u._sa_sigaction
|
||||
|
||||
#else /* __i386__ */
|
||||
|
||||
struct sigaction {
|
||||
__sighandler_t sa_handler;
|
||||
unsigned long sa_flags;
|
||||
__sigrestore_t sa_restorer;
|
||||
sigset_t sa_mask; /* mask last for extensibility */
|
||||
};
|
||||
|
||||
#endif /* !__i386__ */
|
||||
|
||||
typedef struct sigaltstack {
|
||||
void *ss_sp;
|
||||
int ss_flags;
|
||||
size_t ss_size;
|
||||
} stack_t;
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_X86_SIGNAL_H */
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/socket.h>
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/sockios.h>
|
||||
@ -0,0 +1,137 @@
|
||||
#ifndef _ASM_X86_STAT_H
|
||||
#define _ASM_X86_STAT_H
|
||||
|
||||
#include <asm/posix_types.h>
|
||||
|
||||
#define STAT_HAVE_NSEC 1
|
||||
|
||||
#ifdef __i386__
|
||||
struct stat {
|
||||
unsigned long st_dev;
|
||||
unsigned long st_ino;
|
||||
unsigned short st_mode;
|
||||
unsigned short st_nlink;
|
||||
unsigned short st_uid;
|
||||
unsigned short st_gid;
|
||||
unsigned long st_rdev;
|
||||
unsigned long st_size;
|
||||
unsigned long st_blksize;
|
||||
unsigned long st_blocks;
|
||||
unsigned long st_atime;
|
||||
unsigned long st_atime_nsec;
|
||||
unsigned long st_mtime;
|
||||
unsigned long st_mtime_nsec;
|
||||
unsigned long st_ctime;
|
||||
unsigned long st_ctime_nsec;
|
||||
unsigned long __unused4;
|
||||
unsigned long __unused5;
|
||||
};
|
||||
|
||||
/* We don't need to memset the whole thing just to initialize the padding */
|
||||
#define INIT_STRUCT_STAT_PADDING(st) do { \
|
||||
st.__unused4 = 0; \
|
||||
st.__unused5 = 0; \
|
||||
} while (0)
|
||||
|
||||
#define STAT64_HAS_BROKEN_ST_INO 1
|
||||
|
||||
/* This matches struct stat64 in glibc2.1, hence the absolutely
|
||||
* insane amounts of padding around dev_t's.
|
||||
*/
|
||||
struct stat64 {
|
||||
unsigned long long st_dev;
|
||||
unsigned char __pad0[4];
|
||||
|
||||
unsigned long __st_ino;
|
||||
|
||||
unsigned int st_mode;
|
||||
unsigned int st_nlink;
|
||||
|
||||
unsigned long st_uid;
|
||||
unsigned long st_gid;
|
||||
|
||||
unsigned long long st_rdev;
|
||||
unsigned char __pad3[4];
|
||||
|
||||
long long st_size;
|
||||
unsigned long st_blksize;
|
||||
|
||||
/* Number 512-byte blocks allocated. */
|
||||
unsigned long long st_blocks;
|
||||
|
||||
unsigned long st_atime;
|
||||
unsigned long st_atime_nsec;
|
||||
|
||||
unsigned long st_mtime;
|
||||
unsigned int st_mtime_nsec;
|
||||
|
||||
unsigned long st_ctime;
|
||||
unsigned long st_ctime_nsec;
|
||||
|
||||
unsigned long long st_ino;
|
||||
};
|
||||
|
||||
/* We don't need to memset the whole thing just to initialize the padding */
|
||||
#define INIT_STRUCT_STAT64_PADDING(st) do { \
|
||||
memset(&st.__pad0, 0, sizeof(st.__pad0)); \
|
||||
memset(&st.__pad3, 0, sizeof(st.__pad3)); \
|
||||
} while (0)
|
||||
|
||||
#else /* __i386__ */
|
||||
|
||||
struct stat {
|
||||
__kernel_ulong_t st_dev;
|
||||
__kernel_ulong_t st_ino;
|
||||
__kernel_ulong_t st_nlink;
|
||||
|
||||
unsigned int st_mode;
|
||||
unsigned int st_uid;
|
||||
unsigned int st_gid;
|
||||
unsigned int __pad0;
|
||||
__kernel_ulong_t st_rdev;
|
||||
__kernel_long_t st_size;
|
||||
__kernel_long_t st_blksize;
|
||||
__kernel_long_t st_blocks; /* Number 512-byte blocks allocated. */
|
||||
|
||||
__kernel_ulong_t st_atime;
|
||||
__kernel_ulong_t st_atime_nsec;
|
||||
__kernel_ulong_t st_mtime;
|
||||
__kernel_ulong_t st_mtime_nsec;
|
||||
__kernel_ulong_t st_ctime;
|
||||
__kernel_ulong_t st_ctime_nsec;
|
||||
__kernel_long_t __unused[3];
|
||||
};
|
||||
|
||||
/* We don't need to memset the whole thing just to initialize the padding */
|
||||
#define INIT_STRUCT_STAT_PADDING(st) do { \
|
||||
st.__pad0 = 0; \
|
||||
st.__unused[0] = 0; \
|
||||
st.__unused[1] = 0; \
|
||||
st.__unused[2] = 0; \
|
||||
} while (0)
|
||||
|
||||
#endif
|
||||
|
||||
/* for 32bit emulation and 32 bit kernels */
|
||||
struct __old_kernel_stat {
|
||||
unsigned short st_dev;
|
||||
unsigned short st_ino;
|
||||
unsigned short st_mode;
|
||||
unsigned short st_nlink;
|
||||
unsigned short st_uid;
|
||||
unsigned short st_gid;
|
||||
unsigned short st_rdev;
|
||||
#ifdef __i386__
|
||||
unsigned long st_size;
|
||||
unsigned long st_atime;
|
||||
unsigned long st_mtime;
|
||||
unsigned long st_ctime;
|
||||
#else
|
||||
unsigned int st_size;
|
||||
unsigned int st_atime;
|
||||
unsigned int st_mtime;
|
||||
unsigned int st_ctime;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* _ASM_X86_STAT_H */
|
||||
@ -0,0 +1,12 @@
|
||||
#ifndef _ASM_X86_STATFS_H
|
||||
#define _ASM_X86_STATFS_H
|
||||
|
||||
/*
|
||||
* We need compat_statfs64 to be packed, because the i386 ABI won't
|
||||
* add padding at the end to bring it to a multiple of 8 bytes, but
|
||||
* the x86_64 ABI will.
|
||||
*/
|
||||
#define ARCH_PACK_COMPAT_STATFS64 __attribute__((packed,aligned(4)))
|
||||
|
||||
#include <asm-generic/statfs.h>
|
||||
#endif /* _ASM_X86_STATFS_H */
|
||||
@ -0,0 +1,133 @@
|
||||
#ifndef __SVM_H
|
||||
#define __SVM_H
|
||||
|
||||
#define SVM_EXIT_READ_CR0 0x000
|
||||
#define SVM_EXIT_READ_CR3 0x003
|
||||
#define SVM_EXIT_READ_CR4 0x004
|
||||
#define SVM_EXIT_READ_CR8 0x008
|
||||
#define SVM_EXIT_WRITE_CR0 0x010
|
||||
#define SVM_EXIT_WRITE_CR3 0x013
|
||||
#define SVM_EXIT_WRITE_CR4 0x014
|
||||
#define SVM_EXIT_WRITE_CR8 0x018
|
||||
#define SVM_EXIT_READ_DR0 0x020
|
||||
#define SVM_EXIT_READ_DR1 0x021
|
||||
#define SVM_EXIT_READ_DR2 0x022
|
||||
#define SVM_EXIT_READ_DR3 0x023
|
||||
#define SVM_EXIT_READ_DR4 0x024
|
||||
#define SVM_EXIT_READ_DR5 0x025
|
||||
#define SVM_EXIT_READ_DR6 0x026
|
||||
#define SVM_EXIT_READ_DR7 0x027
|
||||
#define SVM_EXIT_WRITE_DR0 0x030
|
||||
#define SVM_EXIT_WRITE_DR1 0x031
|
||||
#define SVM_EXIT_WRITE_DR2 0x032
|
||||
#define SVM_EXIT_WRITE_DR3 0x033
|
||||
#define SVM_EXIT_WRITE_DR4 0x034
|
||||
#define SVM_EXIT_WRITE_DR5 0x035
|
||||
#define SVM_EXIT_WRITE_DR6 0x036
|
||||
#define SVM_EXIT_WRITE_DR7 0x037
|
||||
#define SVM_EXIT_EXCP_BASE 0x040
|
||||
#define SVM_EXIT_INTR 0x060
|
||||
#define SVM_EXIT_NMI 0x061
|
||||
#define SVM_EXIT_SMI 0x062
|
||||
#define SVM_EXIT_INIT 0x063
|
||||
#define SVM_EXIT_VINTR 0x064
|
||||
#define SVM_EXIT_CR0_SEL_WRITE 0x065
|
||||
#define SVM_EXIT_IDTR_READ 0x066
|
||||
#define SVM_EXIT_GDTR_READ 0x067
|
||||
#define SVM_EXIT_LDTR_READ 0x068
|
||||
#define SVM_EXIT_TR_READ 0x069
|
||||
#define SVM_EXIT_IDTR_WRITE 0x06a
|
||||
#define SVM_EXIT_GDTR_WRITE 0x06b
|
||||
#define SVM_EXIT_LDTR_WRITE 0x06c
|
||||
#define SVM_EXIT_TR_WRITE 0x06d
|
||||
#define SVM_EXIT_RDTSC 0x06e
|
||||
#define SVM_EXIT_RDPMC 0x06f
|
||||
#define SVM_EXIT_PUSHF 0x070
|
||||
#define SVM_EXIT_POPF 0x071
|
||||
#define SVM_EXIT_CPUID 0x072
|
||||
#define SVM_EXIT_RSM 0x073
|
||||
#define SVM_EXIT_IRET 0x074
|
||||
#define SVM_EXIT_SWINT 0x075
|
||||
#define SVM_EXIT_INVD 0x076
|
||||
#define SVM_EXIT_PAUSE 0x077
|
||||
#define SVM_EXIT_HLT 0x078
|
||||
#define SVM_EXIT_INVLPG 0x079
|
||||
#define SVM_EXIT_INVLPGA 0x07a
|
||||
#define SVM_EXIT_IOIO 0x07b
|
||||
#define SVM_EXIT_MSR 0x07c
|
||||
#define SVM_EXIT_TASK_SWITCH 0x07d
|
||||
#define SVM_EXIT_FERR_FREEZE 0x07e
|
||||
#define SVM_EXIT_SHUTDOWN 0x07f
|
||||
#define SVM_EXIT_VMRUN 0x080
|
||||
#define SVM_EXIT_VMMCALL 0x081
|
||||
#define SVM_EXIT_VMLOAD 0x082
|
||||
#define SVM_EXIT_VMSAVE 0x083
|
||||
#define SVM_EXIT_STGI 0x084
|
||||
#define SVM_EXIT_CLGI 0x085
|
||||
#define SVM_EXIT_SKINIT 0x086
|
||||
#define SVM_EXIT_RDTSCP 0x087
|
||||
#define SVM_EXIT_ICEBP 0x088
|
||||
#define SVM_EXIT_WBINVD 0x089
|
||||
#define SVM_EXIT_MONITOR 0x08a
|
||||
#define SVM_EXIT_MWAIT 0x08b
|
||||
#define SVM_EXIT_MWAIT_COND 0x08c
|
||||
#define SVM_EXIT_XSETBV 0x08d
|
||||
#define SVM_EXIT_NPF 0x400
|
||||
|
||||
#define SVM_EXIT_ERR -1
|
||||
|
||||
#define SVM_EXIT_REASONS \
|
||||
{ SVM_EXIT_READ_CR0, "read_cr0" }, \
|
||||
{ SVM_EXIT_READ_CR3, "read_cr3" }, \
|
||||
{ SVM_EXIT_READ_CR4, "read_cr4" }, \
|
||||
{ SVM_EXIT_READ_CR8, "read_cr8" }, \
|
||||
{ SVM_EXIT_WRITE_CR0, "write_cr0" }, \
|
||||
{ SVM_EXIT_WRITE_CR3, "write_cr3" }, \
|
||||
{ SVM_EXIT_WRITE_CR4, "write_cr4" }, \
|
||||
{ SVM_EXIT_WRITE_CR8, "write_cr8" }, \
|
||||
{ SVM_EXIT_READ_DR0, "read_dr0" }, \
|
||||
{ SVM_EXIT_READ_DR1, "read_dr1" }, \
|
||||
{ SVM_EXIT_READ_DR2, "read_dr2" }, \
|
||||
{ SVM_EXIT_READ_DR3, "read_dr3" }, \
|
||||
{ SVM_EXIT_WRITE_DR0, "write_dr0" }, \
|
||||
{ SVM_EXIT_WRITE_DR1, "write_dr1" }, \
|
||||
{ SVM_EXIT_WRITE_DR2, "write_dr2" }, \
|
||||
{ SVM_EXIT_WRITE_DR3, "write_dr3" }, \
|
||||
{ SVM_EXIT_WRITE_DR5, "write_dr5" }, \
|
||||
{ SVM_EXIT_WRITE_DR7, "write_dr7" }, \
|
||||
{ SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, \
|
||||
{ SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, \
|
||||
{ SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, \
|
||||
{ SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, \
|
||||
{ SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, \
|
||||
{ SVM_EXIT_EXCP_BASE + AC_VECTOR, "AC excp" }, \
|
||||
{ SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, \
|
||||
{ SVM_EXIT_INTR, "interrupt" }, \
|
||||
{ SVM_EXIT_NMI, "nmi" }, \
|
||||
{ SVM_EXIT_SMI, "smi" }, \
|
||||
{ SVM_EXIT_INIT, "init" }, \
|
||||
{ SVM_EXIT_VINTR, "vintr" }, \
|
||||
{ SVM_EXIT_CPUID, "cpuid" }, \
|
||||
{ SVM_EXIT_INVD, "invd" }, \
|
||||
{ SVM_EXIT_HLT, "hlt" }, \
|
||||
{ SVM_EXIT_INVLPG, "invlpg" }, \
|
||||
{ SVM_EXIT_INVLPGA, "invlpga" }, \
|
||||
{ SVM_EXIT_IOIO, "io" }, \
|
||||
{ SVM_EXIT_MSR, "msr" }, \
|
||||
{ SVM_EXIT_TASK_SWITCH, "task_switch" }, \
|
||||
{ SVM_EXIT_SHUTDOWN, "shutdown" }, \
|
||||
{ SVM_EXIT_VMRUN, "vmrun" }, \
|
||||
{ SVM_EXIT_VMMCALL, "hypercall" }, \
|
||||
{ SVM_EXIT_VMLOAD, "vmload" }, \
|
||||
{ SVM_EXIT_VMSAVE, "vmsave" }, \
|
||||
{ SVM_EXIT_STGI, "stgi" }, \
|
||||
{ SVM_EXIT_CLGI, "clgi" }, \
|
||||
{ SVM_EXIT_SKINIT, "skinit" }, \
|
||||
{ SVM_EXIT_WBINVD, "wbinvd" }, \
|
||||
{ SVM_EXIT_MONITOR, "monitor" }, \
|
||||
{ SVM_EXIT_MWAIT, "mwait" }, \
|
||||
{ SVM_EXIT_XSETBV, "xsetbv" }, \
|
||||
{ SVM_EXIT_NPF, "npf" }
|
||||
|
||||
|
||||
#endif /* __SVM_H */
|
||||
@ -0,0 +1,36 @@
|
||||
#ifndef _ASM_X86_SWAB_H
|
||||
#define _ASM_X86_SWAB_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
|
||||
static __inline__ __u32 __arch_swab32(__u32 val)
|
||||
{
|
||||
__asm__("bswapl %0" : "=r" (val) : "0" (val));
|
||||
return val;
|
||||
}
|
||||
#define __arch_swab32 __arch_swab32
|
||||
|
||||
static __inline__ __u64 __arch_swab64(__u64 val)
|
||||
{
|
||||
#ifdef __i386__
|
||||
union {
|
||||
struct {
|
||||
__u32 a;
|
||||
__u32 b;
|
||||
} s;
|
||||
__u64 u;
|
||||
} v;
|
||||
v.u = val;
|
||||
__asm__("bswapl %0 ; bswapl %1 ; xchgl %0,%1"
|
||||
: "=r" (v.s.a), "=r" (v.s.b)
|
||||
: "0" (v.s.a), "1" (v.s.b));
|
||||
return v.u;
|
||||
#else /* __i386__ */
|
||||
__asm__("bswapq %0" : "=r" (val) : "0" (val));
|
||||
return val;
|
||||
#endif
|
||||
}
|
||||
#define __arch_swab64 __arch_swab64
|
||||
|
||||
#endif /* _ASM_X86_SWAB_H */
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/termbits.h>
|
||||
@ -0,0 +1 @@
|
||||
#include <asm-generic/termios.h>
|
||||
@ -0,0 +1,6 @@
|
||||
#ifndef _ASM_X86_TYPES_H
|
||||
#define _ASM_X86_TYPES_H
|
||||
|
||||
#include <asm-generic/types.h>
|
||||
|
||||
#endif /* _ASM_X86_TYPES_H */
|
||||
@ -0,0 +1,12 @@
|
||||
#ifndef _ASM_X86_UCONTEXT_H
|
||||
#define _ASM_X86_UCONTEXT_H
|
||||
|
||||
#define UC_FP_XSTATE 0x1 /* indicates the presence of extended state
|
||||
* information in the memory layout pointed
|
||||
* by the fpstate pointer in the ucontext's
|
||||
* sigcontext struct (uc_mcontext).
|
||||
*/
|
||||
|
||||
#include <asm-generic/ucontext.h>
|
||||
|
||||
#endif /* _ASM_X86_UCONTEXT_H */
|
||||
@ -0,0 +1,15 @@
|
||||
#ifndef _ASM_X86_UNISTD_H
|
||||
#define _ASM_X86_UNISTD_H
|
||||
|
||||
/* x32 syscall flag bit */
|
||||
#define __X32_SYSCALL_BIT 0x40000000
|
||||
|
||||
# ifdef __i386__
|
||||
# include <asm/unistd_32.h>
|
||||
# elif defined(__ILP32__)
|
||||
# include <asm/unistd_x32.h>
|
||||
# else
|
||||
# include <asm/unistd_64.h>
|
||||
# endif
|
||||
|
||||
#endif /* _ASM_X86_UNISTD_H */
|
||||
@ -0,0 +1,378 @@
|
||||
#ifndef _ASM_X86_UNISTD_32_H
|
||||
#define _ASM_X86_UNISTD_32_H 1
|
||||
|
||||
#define __NR_restart_syscall 0
|
||||
#define __NR_exit 1
|
||||
#define __NR_fork 2
|
||||
#define __NR_read 3
|
||||
#define __NR_write 4
|
||||
#define __NR_open 5
|
||||
#define __NR_close 6
|
||||
#define __NR_waitpid 7
|
||||
#define __NR_creat 8
|
||||
#define __NR_link 9
|
||||
#define __NR_unlink 10
|
||||
#define __NR_execve 11
|
||||
#define __NR_chdir 12
|
||||
#define __NR_time 13
|
||||
#define __NR_mknod 14
|
||||
#define __NR_chmod 15
|
||||
#define __NR_lchown 16
|
||||
#define __NR_break 17
|
||||
#define __NR_oldstat 18
|
||||
#define __NR_lseek 19
|
||||
#define __NR_getpid 20
|
||||
#define __NR_mount 21
|
||||
#define __NR_umount 22
|
||||
#define __NR_setuid 23
|
||||
#define __NR_getuid 24
|
||||
#define __NR_stime 25
|
||||
#define __NR_ptrace 26
|
||||
#define __NR_alarm 27
|
||||
#define __NR_oldfstat 28
|
||||
#define __NR_pause 29
|
||||
#define __NR_utime 30
|
||||
#define __NR_stty 31
|
||||
#define __NR_gtty 32
|
||||
#define __NR_access 33
|
||||
#define __NR_nice 34
|
||||
#define __NR_ftime 35
|
||||
#define __NR_sync 36
|
||||
#define __NR_kill 37
|
||||
#define __NR_rename 38
|
||||
#define __NR_mkdir 39
|
||||
#define __NR_rmdir 40
|
||||
#define __NR_dup 41
|
||||
#define __NR_pipe 42
|
||||
#define __NR_times 43
|
||||
#define __NR_prof 44
|
||||
#define __NR_brk 45
|
||||
#define __NR_setgid 46
|
||||
#define __NR_getgid 47
|
||||
#define __NR_signal 48
|
||||
#define __NR_geteuid 49
|
||||
#define __NR_getegid 50
|
||||
#define __NR_acct 51
|
||||
#define __NR_umount2 52
|
||||
#define __NR_lock 53
|
||||
#define __NR_ioctl 54
|
||||
#define __NR_fcntl 55
|
||||
#define __NR_mpx 56
|
||||
#define __NR_setpgid 57
|
||||
#define __NR_ulimit 58
|
||||
#define __NR_oldolduname 59
|
||||
#define __NR_umask 60
|
||||
#define __NR_chroot 61
|
||||
#define __NR_ustat 62
|
||||
#define __NR_dup2 63
|
||||
#define __NR_getppid 64
|
||||
#define __NR_getpgrp 65
|
||||
#define __NR_setsid 66
|
||||
#define __NR_sigaction 67
|
||||
#define __NR_sgetmask 68
|
||||
#define __NR_ssetmask 69
|
||||
#define __NR_setreuid 70
|
||||
#define __NR_setregid 71
|
||||
#define __NR_sigsuspend 72
|
||||
#define __NR_sigpending 73
|
||||
#define __NR_sethostname 74
|
||||
#define __NR_setrlimit 75
|
||||
#define __NR_getrlimit 76
|
||||
#define __NR_getrusage 77
|
||||
#define __NR_gettimeofday 78
|
||||
#define __NR_settimeofday 79
|
||||
#define __NR_getgroups 80
|
||||
#define __NR_setgroups 81
|
||||
#define __NR_select 82
|
||||
#define __NR_symlink 83
|
||||
#define __NR_oldlstat 84
|
||||
#define __NR_readlink 85
|
||||
#define __NR_uselib 86
|
||||
#define __NR_swapon 87
|
||||
#define __NR_reboot 88
|
||||
#define __NR_readdir 89
|
||||
#define __NR_mmap 90
|
||||
#define __NR_munmap 91
|
||||
#define __NR_truncate 92
|
||||
#define __NR_ftruncate 93
|
||||
#define __NR_fchmod 94
|
||||
#define __NR_fchown 95
|
||||
#define __NR_getpriority 96
|
||||
#define __NR_setpriority 97
|
||||
#define __NR_profil 98
|
||||
#define __NR_statfs 99
|
||||
#define __NR_fstatfs 100
|
||||
#define __NR_ioperm 101
|
||||
#define __NR_socketcall 102
|
||||
#define __NR_syslog 103
|
||||
#define __NR_setitimer 104
|
||||
#define __NR_getitimer 105
|
||||
#define __NR_stat 106
|
||||
#define __NR_lstat 107
|
||||
#define __NR_fstat 108
|
||||
#define __NR_olduname 109
|
||||
#define __NR_iopl 110
|
||||
#define __NR_vhangup 111
|
||||
#define __NR_idle 112
|
||||
#define __NR_vm86old 113
|
||||
#define __NR_wait4 114
|
||||
#define __NR_swapoff 115
|
||||
#define __NR_sysinfo 116
|
||||
#define __NR_ipc 117
|
||||
#define __NR_fsync 118
|
||||
#define __NR_sigreturn 119
|
||||
#define __NR_clone 120
|
||||
#define __NR_setdomainname 121
|
||||
#define __NR_uname 122
|
||||
#define __NR_modify_ldt 123
|
||||
#define __NR_adjtimex 124
|
||||
#define __NR_mprotect 125
|
||||
#define __NR_sigprocmask 126
|
||||
#define __NR_create_module 127
|
||||
#define __NR_init_module 128
|
||||
#define __NR_delete_module 129
|
||||
#define __NR_get_kernel_syms 130
|
||||
#define __NR_quotactl 131
|
||||
#define __NR_getpgid 132
|
||||
#define __NR_fchdir 133
|
||||
#define __NR_bdflush 134
|
||||
#define __NR_sysfs 135
|
||||
#define __NR_personality 136
|
||||
#define __NR_afs_syscall 137
|
||||
#define __NR_setfsuid 138
|
||||
#define __NR_setfsgid 139
|
||||
#define __NR__llseek 140
|
||||
#define __NR_getdents 141
|
||||
#define __NR__newselect 142
|
||||
#define __NR_flock 143
|
||||
#define __NR_msync 144
|
||||
#define __NR_readv 145
|
||||
#define __NR_writev 146
|
||||
#define __NR_getsid 147
|
||||
#define __NR_fdatasync 148
|
||||
#define __NR__sysctl 149
|
||||
#define __NR_mlock 150
|
||||
#define __NR_munlock 151
|
||||
#define __NR_mlockall 152
|
||||
#define __NR_munlockall 153
|
||||
#define __NR_sched_setparam 154
|
||||
#define __NR_sched_getparam 155
|
||||
#define __NR_sched_setscheduler 156
|
||||
#define __NR_sched_getscheduler 157
|
||||
#define __NR_sched_yield 158
|
||||
#define __NR_sched_get_priority_max 159
|
||||
#define __NR_sched_get_priority_min 160
|
||||
#define __NR_sched_rr_get_interval 161
|
||||
#define __NR_nanosleep 162
|
||||
#define __NR_mremap 163
|
||||
#define __NR_setresuid 164
|
||||
#define __NR_getresuid 165
|
||||
#define __NR_vm86 166
|
||||
#define __NR_query_module 167
|
||||
#define __NR_poll 168
|
||||
#define __NR_nfsservctl 169
|
||||
#define __NR_setresgid 170
|
||||
#define __NR_getresgid 171
|
||||
#define __NR_prctl 172
|
||||
#define __NR_rt_sigreturn 173
|
||||
#define __NR_rt_sigaction 174
|
||||
#define __NR_rt_sigprocmask 175
|
||||
#define __NR_rt_sigpending 176
|
||||
#define __NR_rt_sigtimedwait 177
|
||||
#define __NR_rt_sigqueueinfo 178
|
||||
#define __NR_rt_sigsuspend 179
|
||||
#define __NR_pread64 180
|
||||
#define __NR_pwrite64 181
|
||||
#define __NR_chown 182
|
||||
#define __NR_getcwd 183
|
||||
#define __NR_capget 184
|
||||
#define __NR_capset 185
|
||||
#define __NR_sigaltstack 186
|
||||
#define __NR_sendfile 187
|
||||
#define __NR_getpmsg 188
|
||||
#define __NR_putpmsg 189
|
||||
#define __NR_vfork 190
|
||||
#define __NR_ugetrlimit 191
|
||||
#define __NR_mmap2 192
|
||||
#define __NR_truncate64 193
|
||||
#define __NR_ftruncate64 194
|
||||
#define __NR_stat64 195
|
||||
#define __NR_lstat64 196
|
||||
#define __NR_fstat64 197
|
||||
#define __NR_lchown32 198
|
||||
#define __NR_getuid32 199
|
||||
#define __NR_getgid32 200
|
||||
#define __NR_geteuid32 201
|
||||
#define __NR_getegid32 202
|
||||
#define __NR_setreuid32 203
|
||||
#define __NR_setregid32 204
|
||||
#define __NR_getgroups32 205
|
||||
#define __NR_setgroups32 206
|
||||
#define __NR_fchown32 207
|
||||
#define __NR_setresuid32 208
|
||||
#define __NR_getresuid32 209
|
||||
#define __NR_setresgid32 210
|
||||
#define __NR_getresgid32 211
|
||||
#define __NR_chown32 212
|
||||
#define __NR_setuid32 213
|
||||
#define __NR_setgid32 214
|
||||
#define __NR_setfsuid32 215
|
||||
#define __NR_setfsgid32 216
|
||||
#define __NR_pivot_root 217
|
||||
#define __NR_mincore 218
|
||||
#define __NR_madvise 219
|
||||
#define __NR_getdents64 220
|
||||
#define __NR_fcntl64 221
|
||||
#define __NR_gettid 224
|
||||
#define __NR_readahead 225
|
||||
#define __NR_setxattr 226
|
||||
#define __NR_lsetxattr 227
|
||||
#define __NR_fsetxattr 228
|
||||
#define __NR_getxattr 229
|
||||
#define __NR_lgetxattr 230
|
||||
#define __NR_fgetxattr 231
|
||||
#define __NR_listxattr 232
|
||||
#define __NR_llistxattr 233
|
||||
#define __NR_flistxattr 234
|
||||
#define __NR_removexattr 235
|
||||
#define __NR_lremovexattr 236
|
||||
#define __NR_fremovexattr 237
|
||||
#define __NR_tkill 238
|
||||
#define __NR_sendfile64 239
|
||||
#define __NR_futex 240
|
||||
#define __NR_sched_setaffinity 241
|
||||
#define __NR_sched_getaffinity 242
|
||||
#define __NR_set_thread_area 243
|
||||
#define __NR_get_thread_area 244
|
||||
#define __NR_io_setup 245
|
||||
#define __NR_io_destroy 246
|
||||
#define __NR_io_getevents 247
|
||||
#define __NR_io_submit 248
|
||||
#define __NR_io_cancel 249
|
||||
#define __NR_fadvise64 250
|
||||
#define __NR_exit_group 252
|
||||
#define __NR_lookup_dcookie 253
|
||||
#define __NR_epoll_create 254
|
||||
#define __NR_epoll_ctl 255
|
||||
#define __NR_epoll_wait 256
|
||||
#define __NR_remap_file_pages 257
|
||||
#define __NR_set_tid_address 258
|
||||
#define __NR_timer_create 259
|
||||
#define __NR_timer_settime 260
|
||||
#define __NR_timer_gettime 261
|
||||
#define __NR_timer_getoverrun 262
|
||||
#define __NR_timer_delete 263
|
||||
#define __NR_clock_settime 264
|
||||
#define __NR_clock_gettime 265
|
||||
#define __NR_clock_getres 266
|
||||
#define __NR_clock_nanosleep 267
|
||||
#define __NR_statfs64 268
|
||||
#define __NR_fstatfs64 269
|
||||
#define __NR_tgkill 270
|
||||
#define __NR_utimes 271
|
||||
#define __NR_fadvise64_64 272
|
||||
#define __NR_vserver 273
|
||||
#define __NR_mbind 274
|
||||
#define __NR_get_mempolicy 275
|
||||
#define __NR_set_mempolicy 276
|
||||
#define __NR_mq_open 277
|
||||
#define __NR_mq_unlink 278
|
||||
#define __NR_mq_timedsend 279
|
||||
#define __NR_mq_timedreceive 280
|
||||
#define __NR_mq_notify 281
|
||||
#define __NR_mq_getsetattr 282
|
||||
#define __NR_kexec_load 283
|
||||
#define __NR_waitid 284
|
||||
#define __NR_add_key 286
|
||||
#define __NR_request_key 287
|
||||
#define __NR_keyctl 288
|
||||
#define __NR_ioprio_set 289
|
||||
#define __NR_ioprio_get 290
|
||||
#define __NR_inotify_init 291
|
||||
#define __NR_inotify_add_watch 292
|
||||
#define __NR_inotify_rm_watch 293
|
||||
#define __NR_migrate_pages 294
|
||||
#define __NR_openat 295
|
||||
#define __NR_mkdirat 296
|
||||
#define __NR_mknodat 297
|
||||
#define __NR_fchownat 298
|
||||
#define __NR_futimesat 299
|
||||
#define __NR_fstatat64 300
|
||||
#define __NR_unlinkat 301
|
||||
#define __NR_renameat 302
|
||||
#define __NR_linkat 303
|
||||
#define __NR_symlinkat 304
|
||||
#define __NR_readlinkat 305
|
||||
#define __NR_fchmodat 306
|
||||
#define __NR_faccessat 307
|
||||
#define __NR_pselect6 308
|
||||
#define __NR_ppoll 309
|
||||
#define __NR_unshare 310
|
||||
#define __NR_set_robust_list 311
|
||||
#define __NR_get_robust_list 312
|
||||
#define __NR_splice 313
|
||||
#define __NR_sync_file_range 314
|
||||
#define __NR_tee 315
|
||||
#define __NR_vmsplice 316
|
||||
#define __NR_move_pages 317
|
||||
#define __NR_getcpu 318
|
||||
#define __NR_epoll_pwait 319
|
||||
#define __NR_utimensat 320
|
||||
#define __NR_signalfd 321
|
||||
#define __NR_timerfd_create 322
|
||||
#define __NR_eventfd 323
|
||||
#define __NR_fallocate 324
|
||||
#define __NR_timerfd_settime 325
|
||||
#define __NR_timerfd_gettime 326
|
||||
#define __NR_signalfd4 327
|
||||
#define __NR_eventfd2 328
|
||||
#define __NR_epoll_create1 329
|
||||
#define __NR_dup3 330
|
||||
#define __NR_pipe2 331
|
||||
#define __NR_inotify_init1 332
|
||||
#define __NR_preadv 333
|
||||
#define __NR_pwritev 334
|
||||
#define __NR_rt_tgsigqueueinfo 335
|
||||
#define __NR_perf_event_open 336
|
||||
#define __NR_recvmmsg 337
|
||||
#define __NR_fanotify_init 338
|
||||
#define __NR_fanotify_mark 339
|
||||
#define __NR_prlimit64 340
|
||||
#define __NR_name_to_handle_at 341
|
||||
#define __NR_open_by_handle_at 342
|
||||
#define __NR_clock_adjtime 343
|
||||
#define __NR_syncfs 344
|
||||
#define __NR_sendmmsg 345
|
||||
#define __NR_setns 346
|
||||
#define __NR_process_vm_readv 347
|
||||
#define __NR_process_vm_writev 348
|
||||
#define __NR_kcmp 349
|
||||
#define __NR_finit_module 350
|
||||
#define __NR_sched_setattr 351
|
||||
#define __NR_sched_getattr 352
|
||||
#define __NR_renameat2 353
|
||||
#define __NR_seccomp 354
|
||||
#define __NR_getrandom 355
|
||||
#define __NR_memfd_create 356
|
||||
#define __NR_bpf 357
|
||||
#define __NR_execveat 358
|
||||
#define __NR_socket 359
|
||||
#define __NR_socketpair 360
|
||||
#define __NR_bind 361
|
||||
#define __NR_connect 362
|
||||
#define __NR_listen 363
|
||||
#define __NR_accept4 364
|
||||
#define __NR_getsockopt 365
|
||||
#define __NR_setsockopt 366
|
||||
#define __NR_getsockname 367
|
||||
#define __NR_getpeername 368
|
||||
#define __NR_sendto 369
|
||||
#define __NR_sendmsg 370
|
||||
#define __NR_recvfrom 371
|
||||
#define __NR_recvmsg 372
|
||||
#define __NR_shutdown 373
|
||||
#define __NR_userfaultfd 374
|
||||
#define __NR_membarrier 375
|
||||
#define __NR_mlock2 376
|
||||
|
||||
#endif /* _ASM_X86_UNISTD_32_H */
|
||||
@ -0,0 +1,331 @@
|
||||
#ifndef _ASM_X86_UNISTD_64_H
|
||||
#define _ASM_X86_UNISTD_64_H 1
|
||||
|
||||
#define __NR_read 0
|
||||
#define __NR_write 1
|
||||
#define __NR_open 2
|
||||
#define __NR_close 3
|
||||
#define __NR_stat 4
|
||||
#define __NR_fstat 5
|
||||
#define __NR_lstat 6
|
||||
#define __NR_poll 7
|
||||
#define __NR_lseek 8
|
||||
#define __NR_mmap 9
|
||||
#define __NR_mprotect 10
|
||||
#define __NR_munmap 11
|
||||
#define __NR_brk 12
|
||||
#define __NR_rt_sigaction 13
|
||||
#define __NR_rt_sigprocmask 14
|
||||
#define __NR_rt_sigreturn 15
|
||||
#define __NR_ioctl 16
|
||||
#define __NR_pread64 17
|
||||
#define __NR_pwrite64 18
|
||||
#define __NR_readv 19
|
||||
#define __NR_writev 20
|
||||
#define __NR_access 21
|
||||
#define __NR_pipe 22
|
||||
#define __NR_select 23
|
||||
#define __NR_sched_yield 24
|
||||
#define __NR_mremap 25
|
||||
#define __NR_msync 26
|
||||
#define __NR_mincore 27
|
||||
#define __NR_madvise 28
|
||||
#define __NR_shmget 29
|
||||
#define __NR_shmat 30
|
||||
#define __NR_shmctl 31
|
||||
#define __NR_dup 32
|
||||
#define __NR_dup2 33
|
||||
#define __NR_pause 34
|
||||
#define __NR_nanosleep 35
|
||||
#define __NR_getitimer 36
|
||||
#define __NR_alarm 37
|
||||
#define __NR_setitimer 38
|
||||
#define __NR_getpid 39
|
||||
#define __NR_sendfile 40
|
||||
#define __NR_socket 41
|
||||
#define __NR_connect 42
|
||||
#define __NR_accept 43
|
||||
#define __NR_sendto 44
|
||||
#define __NR_recvfrom 45
|
||||
#define __NR_sendmsg 46
|
||||
#define __NR_recvmsg 47
|
||||
#define __NR_shutdown 48
|
||||
#define __NR_bind 49
|
||||
#define __NR_listen 50
|
||||
#define __NR_getsockname 51
|
||||
#define __NR_getpeername 52
|
||||
#define __NR_socketpair 53
|
||||
#define __NR_setsockopt 54
|
||||
#define __NR_getsockopt 55
|
||||
#define __NR_clone 56
|
||||
#define __NR_fork 57
|
||||
#define __NR_vfork 58
|
||||
#define __NR_execve 59
|
||||
#define __NR_exit 60
|
||||
#define __NR_wait4 61
|
||||
#define __NR_kill 62
|
||||
#define __NR_uname 63
|
||||
#define __NR_semget 64
|
||||
#define __NR_semop 65
|
||||
#define __NR_semctl 66
|
||||
#define __NR_shmdt 67
|
||||
#define __NR_msgget 68
|
||||
#define __NR_msgsnd 69
|
||||
#define __NR_msgrcv 70
|
||||
#define __NR_msgctl 71
|
||||
#define __NR_fcntl 72
|
||||
#define __NR_flock 73
|
||||
#define __NR_fsync 74
|
||||
#define __NR_fdatasync 75
|
||||
#define __NR_truncate 76
|
||||
#define __NR_ftruncate 77
|
||||
#define __NR_getdents 78
|
||||
#define __NR_getcwd 79
|
||||
#define __NR_chdir 80
|
||||
#define __NR_fchdir 81
|
||||
#define __NR_rename 82
|
||||
#define __NR_mkdir 83
|
||||
#define __NR_rmdir 84
|
||||
#define __NR_creat 85
|
||||
#define __NR_link 86
|
||||
#define __NR_unlink 87
|
||||
#define __NR_symlink 88
|
||||
#define __NR_readlink 89
|
||||
#define __NR_chmod 90
|
||||
#define __NR_fchmod 91
|
||||
#define __NR_chown 92
|
||||
#define __NR_fchown 93
|
||||
#define __NR_lchown 94
|
||||
#define __NR_umask 95
|
||||
#define __NR_gettimeofday 96
|
||||
#define __NR_getrlimit 97
|
||||
#define __NR_getrusage 98
|
||||
#define __NR_sysinfo 99
|
||||
#define __NR_times 100
|
||||
#define __NR_ptrace 101
|
||||
#define __NR_getuid 102
|
||||
#define __NR_syslog 103
|
||||
#define __NR_getgid 104
|
||||
#define __NR_setuid 105
|
||||
#define __NR_setgid 106
|
||||
#define __NR_geteuid 107
|
||||
#define __NR_getegid 108
|
||||
#define __NR_setpgid 109
|
||||
#define __NR_getppid 110
|
||||
#define __NR_getpgrp 111
|
||||
#define __NR_setsid 112
|
||||
#define __NR_setreuid 113
|
||||
#define __NR_setregid 114
|
||||
#define __NR_getgroups 115
|
||||
#define __NR_setgroups 116
|
||||
#define __NR_setresuid 117
|
||||
#define __NR_getresuid 118
|
||||
#define __NR_setresgid 119
|
||||
#define __NR_getresgid 120
|
||||
#define __NR_getpgid 121
|
||||
#define __NR_setfsuid 122
|
||||
#define __NR_setfsgid 123
|
||||
#define __NR_getsid 124
|
||||
#define __NR_capget 125
|
||||
#define __NR_capset 126
|
||||
#define __NR_rt_sigpending 127
|
||||
#define __NR_rt_sigtimedwait 128
|
||||
#define __NR_rt_sigqueueinfo 129
|
||||
#define __NR_rt_sigsuspend 130
|
||||
#define __NR_sigaltstack 131
|
||||
#define __NR_utime 132
|
||||
#define __NR_mknod 133
|
||||
#define __NR_uselib 134
|
||||
#define __NR_personality 135
|
||||
#define __NR_ustat 136
|
||||
#define __NR_statfs 137
|
||||
#define __NR_fstatfs 138
|
||||
#define __NR_sysfs 139
|
||||
#define __NR_getpriority 140
|
||||
#define __NR_setpriority 141
|
||||
#define __NR_sched_setparam 142
|
||||
#define __NR_sched_getparam 143
|
||||
#define __NR_sched_setscheduler 144
|
||||
#define __NR_sched_getscheduler 145
|
||||
#define __NR_sched_get_priority_max 146
|
||||
#define __NR_sched_get_priority_min 147
|
||||
#define __NR_sched_rr_get_interval 148
|
||||
#define __NR_mlock 149
|
||||
#define __NR_munlock 150
|
||||
#define __NR_mlockall 151
|
||||
#define __NR_munlockall 152
|
||||
#define __NR_vhangup 153
|
||||
#define __NR_modify_ldt 154
|
||||
#define __NR_pivot_root 155
|
||||
#define __NR__sysctl 156
|
||||
#define __NR_prctl 157
|
||||
#define __NR_arch_prctl 158
|
||||
#define __NR_adjtimex 159
|
||||
#define __NR_setrlimit 160
|
||||
#define __NR_chroot 161
|
||||
#define __NR_sync 162
|
||||
#define __NR_acct 163
|
||||
#define __NR_settimeofday 164
|
||||
#define __NR_mount 165
|
||||
#define __NR_umount2 166
|
||||
#define __NR_swapon 167
|
||||
#define __NR_swapoff 168
|
||||
#define __NR_reboot 169
|
||||
#define __NR_sethostname 170
|
||||
#define __NR_setdomainname 171
|
||||
#define __NR_iopl 172
|
||||
#define __NR_ioperm 173
|
||||
#define __NR_create_module 174
|
||||
#define __NR_init_module 175
|
||||
#define __NR_delete_module 176
|
||||
#define __NR_get_kernel_syms 177
|
||||
#define __NR_query_module 178
|
||||
#define __NR_quotactl 179
|
||||
#define __NR_nfsservctl 180
|
||||
#define __NR_getpmsg 181
|
||||
#define __NR_putpmsg 182
|
||||
#define __NR_afs_syscall 183
|
||||
#define __NR_tuxcall 184
|
||||
#define __NR_security 185
|
||||
#define __NR_gettid 186
|
||||
#define __NR_readahead 187
|
||||
#define __NR_setxattr 188
|
||||
#define __NR_lsetxattr 189
|
||||
#define __NR_fsetxattr 190
|
||||
#define __NR_getxattr 191
|
||||
#define __NR_lgetxattr 192
|
||||
#define __NR_fgetxattr 193
|
||||
#define __NR_listxattr 194
|
||||
#define __NR_llistxattr 195
|
||||
#define __NR_flistxattr 196
|
||||
#define __NR_removexattr 197
|
||||
#define __NR_lremovexattr 198
|
||||
#define __NR_fremovexattr 199
|
||||
#define __NR_tkill 200
|
||||
#define __NR_time 201
|
||||
#define __NR_futex 202
|
||||
#define __NR_sched_setaffinity 203
|
||||
#define __NR_sched_getaffinity 204
|
||||
#define __NR_set_thread_area 205
|
||||
#define __NR_io_setup 206
|
||||
#define __NR_io_destroy 207
|
||||
#define __NR_io_getevents 208
|
||||
#define __NR_io_submit 209
|
||||
#define __NR_io_cancel 210
|
||||
#define __NR_get_thread_area 211
|
||||
#define __NR_lookup_dcookie 212
|
||||
#define __NR_epoll_create 213
|
||||
#define __NR_epoll_ctl_old 214
|
||||
#define __NR_epoll_wait_old 215
|
||||
#define __NR_remap_file_pages 216
|
||||
#define __NR_getdents64 217
|
||||
#define __NR_set_tid_address 218
|
||||
#define __NR_restart_syscall 219
|
||||
#define __NR_semtimedop 220
|
||||
#define __NR_fadvise64 221
|
||||
#define __NR_timer_create 222
|
||||
#define __NR_timer_settime 223
|
||||
#define __NR_timer_gettime 224
|
||||
#define __NR_timer_getoverrun 225
|
||||
#define __NR_timer_delete 226
|
||||
#define __NR_clock_settime 227
|
||||
#define __NR_clock_gettime 228
|
||||
#define __NR_clock_getres 229
|
||||
#define __NR_clock_nanosleep 230
|
||||
#define __NR_exit_group 231
|
||||
#define __NR_epoll_wait 232
|
||||
#define __NR_epoll_ctl 233
|
||||
#define __NR_tgkill 234
|
||||
#define __NR_utimes 235
|
||||
#define __NR_vserver 236
|
||||
#define __NR_mbind 237
|
||||
#define __NR_set_mempolicy 238
|
||||
#define __NR_get_mempolicy 239
|
||||
#define __NR_mq_open 240
|
||||
#define __NR_mq_unlink 241
|
||||
#define __NR_mq_timedsend 242
|
||||
#define __NR_mq_timedreceive 243
|
||||
#define __NR_mq_notify 244
|
||||
#define __NR_mq_getsetattr 245
|
||||
#define __NR_kexec_load 246
|
||||
#define __NR_waitid 247
|
||||
#define __NR_add_key 248
|
||||
#define __NR_request_key 249
|
||||
#define __NR_keyctl 250
|
||||
#define __NR_ioprio_set 251
|
||||
#define __NR_ioprio_get 252
|
||||
#define __NR_inotify_init 253
|
||||
#define __NR_inotify_add_watch 254
|
||||
#define __NR_inotify_rm_watch 255
|
||||
#define __NR_migrate_pages 256
|
||||
#define __NR_openat 257
|
||||
#define __NR_mkdirat 258
|
||||
#define __NR_mknodat 259
|
||||
#define __NR_fchownat 260
|
||||
#define __NR_futimesat 261
|
||||
#define __NR_newfstatat 262
|
||||
#define __NR_unlinkat 263
|
||||
#define __NR_renameat 264
|
||||
#define __NR_linkat 265
|
||||
#define __NR_symlinkat 266
|
||||
#define __NR_readlinkat 267
|
||||
#define __NR_fchmodat 268
|
||||
#define __NR_faccessat 269
|
||||
#define __NR_pselect6 270
|
||||
#define __NR_ppoll 271
|
||||
#define __NR_unshare 272
|
||||
#define __NR_set_robust_list 273
|
||||
#define __NR_get_robust_list 274
|
||||
#define __NR_splice 275
|
||||
#define __NR_tee 276
|
||||
#define __NR_sync_file_range 277
|
||||
#define __NR_vmsplice 278
|
||||
#define __NR_move_pages 279
|
||||
#define __NR_utimensat 280
|
||||
#define __NR_epoll_pwait 281
|
||||
#define __NR_signalfd 282
|
||||
#define __NR_timerfd_create 283
|
||||
#define __NR_eventfd 284
|
||||
#define __NR_fallocate 285
|
||||
#define __NR_timerfd_settime 286
|
||||
#define __NR_timerfd_gettime 287
|
||||
#define __NR_accept4 288
|
||||
#define __NR_signalfd4 289
|
||||
#define __NR_eventfd2 290
|
||||
#define __NR_epoll_create1 291
|
||||
#define __NR_dup3 292
|
||||
#define __NR_pipe2 293
|
||||
#define __NR_inotify_init1 294
|
||||
#define __NR_preadv 295
|
||||
#define __NR_pwritev 296
|
||||
#define __NR_rt_tgsigqueueinfo 297
|
||||
#define __NR_perf_event_open 298
|
||||
#define __NR_recvmmsg 299
|
||||
#define __NR_fanotify_init 300
|
||||
#define __NR_fanotify_mark 301
|
||||
#define __NR_prlimit64 302
|
||||
#define __NR_name_to_handle_at 303
|
||||
#define __NR_open_by_handle_at 304
|
||||
#define __NR_clock_adjtime 305
|
||||
#define __NR_syncfs 306
|
||||
#define __NR_sendmmsg 307
|
||||
#define __NR_setns 308
|
||||
#define __NR_getcpu 309
|
||||
#define __NR_process_vm_readv 310
|
||||
#define __NR_process_vm_writev 311
|
||||
#define __NR_kcmp 312
|
||||
#define __NR_finit_module 313
|
||||
#define __NR_sched_setattr 314
|
||||
#define __NR_sched_getattr 315
|
||||
#define __NR_renameat2 316
|
||||
#define __NR_seccomp 317
|
||||
#define __NR_getrandom 318
|
||||
#define __NR_memfd_create 319
|
||||
#define __NR_kexec_file_load 320
|
||||
#define __NR_bpf 321
|
||||
#define __NR_execveat 322
|
||||
#define __NR_userfaultfd 323
|
||||
#define __NR_membarrier 324
|
||||
#define __NR_mlock2 325
|
||||
|
||||
#endif /* _ASM_X86_UNISTD_64_H */
|
||||
@ -0,0 +1,320 @@
|
||||
#ifndef _ASM_X86_UNISTD_X32_H
|
||||
#define _ASM_X86_UNISTD_X32_H 1
|
||||
|
||||
#define __NR_read (__X32_SYSCALL_BIT + 0)
|
||||
#define __NR_write (__X32_SYSCALL_BIT + 1)
|
||||
#define __NR_open (__X32_SYSCALL_BIT + 2)
|
||||
#define __NR_close (__X32_SYSCALL_BIT + 3)
|
||||
#define __NR_stat (__X32_SYSCALL_BIT + 4)
|
||||
#define __NR_fstat (__X32_SYSCALL_BIT + 5)
|
||||
#define __NR_lstat (__X32_SYSCALL_BIT + 6)
|
||||
#define __NR_poll (__X32_SYSCALL_BIT + 7)
|
||||
#define __NR_lseek (__X32_SYSCALL_BIT + 8)
|
||||
#define __NR_mmap (__X32_SYSCALL_BIT + 9)
|
||||
#define __NR_mprotect (__X32_SYSCALL_BIT + 10)
|
||||
#define __NR_munmap (__X32_SYSCALL_BIT + 11)
|
||||
#define __NR_brk (__X32_SYSCALL_BIT + 12)
|
||||
#define __NR_rt_sigprocmask (__X32_SYSCALL_BIT + 14)
|
||||
#define __NR_pread64 (__X32_SYSCALL_BIT + 17)
|
||||
#define __NR_pwrite64 (__X32_SYSCALL_BIT + 18)
|
||||
#define __NR_access (__X32_SYSCALL_BIT + 21)
|
||||
#define __NR_pipe (__X32_SYSCALL_BIT + 22)
|
||||
#define __NR_select (__X32_SYSCALL_BIT + 23)
|
||||
#define __NR_sched_yield (__X32_SYSCALL_BIT + 24)
|
||||
#define __NR_mremap (__X32_SYSCALL_BIT + 25)
|
||||
#define __NR_msync (__X32_SYSCALL_BIT + 26)
|
||||
#define __NR_mincore (__X32_SYSCALL_BIT + 27)
|
||||
#define __NR_madvise (__X32_SYSCALL_BIT + 28)
|
||||
#define __NR_shmget (__X32_SYSCALL_BIT + 29)
|
||||
#define __NR_shmat (__X32_SYSCALL_BIT + 30)
|
||||
#define __NR_shmctl (__X32_SYSCALL_BIT + 31)
|
||||
#define __NR_dup (__X32_SYSCALL_BIT + 32)
|
||||
#define __NR_dup2 (__X32_SYSCALL_BIT + 33)
|
||||
#define __NR_pause (__X32_SYSCALL_BIT + 34)
|
||||
#define __NR_nanosleep (__X32_SYSCALL_BIT + 35)
|
||||
#define __NR_getitimer (__X32_SYSCALL_BIT + 36)
|
||||
#define __NR_alarm (__X32_SYSCALL_BIT + 37)
|
||||
#define __NR_setitimer (__X32_SYSCALL_BIT + 38)
|
||||
#define __NR_getpid (__X32_SYSCALL_BIT + 39)
|
||||
#define __NR_sendfile (__X32_SYSCALL_BIT + 40)
|
||||
#define __NR_socket (__X32_SYSCALL_BIT + 41)
|
||||
#define __NR_connect (__X32_SYSCALL_BIT + 42)
|
||||
#define __NR_accept (__X32_SYSCALL_BIT + 43)
|
||||
#define __NR_sendto (__X32_SYSCALL_BIT + 44)
|
||||
#define __NR_shutdown (__X32_SYSCALL_BIT + 48)
|
||||
#define __NR_bind (__X32_SYSCALL_BIT + 49)
|
||||
#define __NR_listen (__X32_SYSCALL_BIT + 50)
|
||||
#define __NR_getsockname (__X32_SYSCALL_BIT + 51)
|
||||
#define __NR_getpeername (__X32_SYSCALL_BIT + 52)
|
||||
#define __NR_socketpair (__X32_SYSCALL_BIT + 53)
|
||||
#define __NR_clone (__X32_SYSCALL_BIT + 56)
|
||||
#define __NR_fork (__X32_SYSCALL_BIT + 57)
|
||||
#define __NR_vfork (__X32_SYSCALL_BIT + 58)
|
||||
#define __NR_exit (__X32_SYSCALL_BIT + 60)
|
||||
#define __NR_wait4 (__X32_SYSCALL_BIT + 61)
|
||||
#define __NR_kill (__X32_SYSCALL_BIT + 62)
|
||||
#define __NR_uname (__X32_SYSCALL_BIT + 63)
|
||||
#define __NR_semget (__X32_SYSCALL_BIT + 64)
|
||||
#define __NR_semop (__X32_SYSCALL_BIT + 65)
|
||||
#define __NR_semctl (__X32_SYSCALL_BIT + 66)
|
||||
#define __NR_shmdt (__X32_SYSCALL_BIT + 67)
|
||||
#define __NR_msgget (__X32_SYSCALL_BIT + 68)
|
||||
#define __NR_msgsnd (__X32_SYSCALL_BIT + 69)
|
||||
#define __NR_msgrcv (__X32_SYSCALL_BIT + 70)
|
||||
#define __NR_msgctl (__X32_SYSCALL_BIT + 71)
|
||||
#define __NR_fcntl (__X32_SYSCALL_BIT + 72)
|
||||
#define __NR_flock (__X32_SYSCALL_BIT + 73)
|
||||
#define __NR_fsync (__X32_SYSCALL_BIT + 74)
|
||||
#define __NR_fdatasync (__X32_SYSCALL_BIT + 75)
|
||||
#define __NR_truncate (__X32_SYSCALL_BIT + 76)
|
||||
#define __NR_ftruncate (__X32_SYSCALL_BIT + 77)
|
||||
#define __NR_getdents (__X32_SYSCALL_BIT + 78)
|
||||
#define __NR_getcwd (__X32_SYSCALL_BIT + 79)
|
||||
#define __NR_chdir (__X32_SYSCALL_BIT + 80)
|
||||
#define __NR_fchdir (__X32_SYSCALL_BIT + 81)
|
||||
#define __NR_rename (__X32_SYSCALL_BIT + 82)
|
||||
#define __NR_mkdir (__X32_SYSCALL_BIT + 83)
|
||||
#define __NR_rmdir (__X32_SYSCALL_BIT + 84)
|
||||
#define __NR_creat (__X32_SYSCALL_BIT + 85)
|
||||
#define __NR_link (__X32_SYSCALL_BIT + 86)
|
||||
#define __NR_unlink (__X32_SYSCALL_BIT + 87)
|
||||
#define __NR_symlink (__X32_SYSCALL_BIT + 88)
|
||||
#define __NR_readlink (__X32_SYSCALL_BIT + 89)
|
||||
#define __NR_chmod (__X32_SYSCALL_BIT + 90)
|
||||
#define __NR_fchmod (__X32_SYSCALL_BIT + 91)
|
||||
#define __NR_chown (__X32_SYSCALL_BIT + 92)
|
||||
#define __NR_fchown (__X32_SYSCALL_BIT + 93)
|
||||
#define __NR_lchown (__X32_SYSCALL_BIT + 94)
|
||||
#define __NR_umask (__X32_SYSCALL_BIT + 95)
|
||||
#define __NR_gettimeofday (__X32_SYSCALL_BIT + 96)
|
||||
#define __NR_getrlimit (__X32_SYSCALL_BIT + 97)
|
||||
#define __NR_getrusage (__X32_SYSCALL_BIT + 98)
|
||||
#define __NR_sysinfo (__X32_SYSCALL_BIT + 99)
|
||||
#define __NR_times (__X32_SYSCALL_BIT + 100)
|
||||
#define __NR_getuid (__X32_SYSCALL_BIT + 102)
|
||||
#define __NR_syslog (__X32_SYSCALL_BIT + 103)
|
||||
#define __NR_getgid (__X32_SYSCALL_BIT + 104)
|
||||
#define __NR_setuid (__X32_SYSCALL_BIT + 105)
|
||||
#define __NR_setgid (__X32_SYSCALL_BIT + 106)
|
||||
#define __NR_geteuid (__X32_SYSCALL_BIT + 107)
|
||||
#define __NR_getegid (__X32_SYSCALL_BIT + 108)
|
||||
#define __NR_setpgid (__X32_SYSCALL_BIT + 109)
|
||||
#define __NR_getppid (__X32_SYSCALL_BIT + 110)
|
||||
#define __NR_getpgrp (__X32_SYSCALL_BIT + 111)
|
||||
#define __NR_setsid (__X32_SYSCALL_BIT + 112)
|
||||
#define __NR_setreuid (__X32_SYSCALL_BIT + 113)
|
||||
#define __NR_setregid (__X32_SYSCALL_BIT + 114)
|
||||
#define __NR_getgroups (__X32_SYSCALL_BIT + 115)
|
||||
#define __NR_setgroups (__X32_SYSCALL_BIT + 116)
|
||||
#define __NR_setresuid (__X32_SYSCALL_BIT + 117)
|
||||
#define __NR_getresuid (__X32_SYSCALL_BIT + 118)
|
||||
#define __NR_setresgid (__X32_SYSCALL_BIT + 119)
|
||||
#define __NR_getresgid (__X32_SYSCALL_BIT + 120)
|
||||
#define __NR_getpgid (__X32_SYSCALL_BIT + 121)
|
||||
#define __NR_setfsuid (__X32_SYSCALL_BIT + 122)
|
||||
#define __NR_setfsgid (__X32_SYSCALL_BIT + 123)
|
||||
#define __NR_getsid (__X32_SYSCALL_BIT + 124)
|
||||
#define __NR_capget (__X32_SYSCALL_BIT + 125)
|
||||
#define __NR_capset (__X32_SYSCALL_BIT + 126)
|
||||
#define __NR_rt_sigsuspend (__X32_SYSCALL_BIT + 130)
|
||||
#define __NR_utime (__X32_SYSCALL_BIT + 132)
|
||||
#define __NR_mknod (__X32_SYSCALL_BIT + 133)
|
||||
#define __NR_personality (__X32_SYSCALL_BIT + 135)
|
||||
#define __NR_ustat (__X32_SYSCALL_BIT + 136)
|
||||
#define __NR_statfs (__X32_SYSCALL_BIT + 137)
|
||||
#define __NR_fstatfs (__X32_SYSCALL_BIT + 138)
|
||||
#define __NR_sysfs (__X32_SYSCALL_BIT + 139)
|
||||
#define __NR_getpriority (__X32_SYSCALL_BIT + 140)
|
||||
#define __NR_setpriority (__X32_SYSCALL_BIT + 141)
|
||||
#define __NR_sched_setparam (__X32_SYSCALL_BIT + 142)
|
||||
#define __NR_sched_getparam (__X32_SYSCALL_BIT + 143)
|
||||
#define __NR_sched_setscheduler (__X32_SYSCALL_BIT + 144)
|
||||
#define __NR_sched_getscheduler (__X32_SYSCALL_BIT + 145)
|
||||
#define __NR_sched_get_priority_max (__X32_SYSCALL_BIT + 146)
|
||||
#define __NR_sched_get_priority_min (__X32_SYSCALL_BIT + 147)
|
||||
#define __NR_sched_rr_get_interval (__X32_SYSCALL_BIT + 148)
|
||||
#define __NR_mlock (__X32_SYSCALL_BIT + 149)
|
||||
#define __NR_munlock (__X32_SYSCALL_BIT + 150)
|
||||
#define __NR_mlockall (__X32_SYSCALL_BIT + 151)
|
||||
#define __NR_munlockall (__X32_SYSCALL_BIT + 152)
|
||||
#define __NR_vhangup (__X32_SYSCALL_BIT + 153)
|
||||
#define __NR_modify_ldt (__X32_SYSCALL_BIT + 154)
|
||||
#define __NR_pivot_root (__X32_SYSCALL_BIT + 155)
|
||||
#define __NR_prctl (__X32_SYSCALL_BIT + 157)
|
||||
#define __NR_arch_prctl (__X32_SYSCALL_BIT + 158)
|
||||
#define __NR_adjtimex (__X32_SYSCALL_BIT + 159)
|
||||
#define __NR_setrlimit (__X32_SYSCALL_BIT + 160)
|
||||
#define __NR_chroot (__X32_SYSCALL_BIT + 161)
|
||||
#define __NR_sync (__X32_SYSCALL_BIT + 162)
|
||||
#define __NR_acct (__X32_SYSCALL_BIT + 163)
|
||||
#define __NR_settimeofday (__X32_SYSCALL_BIT + 164)
|
||||
#define __NR_mount (__X32_SYSCALL_BIT + 165)
|
||||
#define __NR_umount2 (__X32_SYSCALL_BIT + 166)
|
||||
#define __NR_swapon (__X32_SYSCALL_BIT + 167)
|
||||
#define __NR_swapoff (__X32_SYSCALL_BIT + 168)
|
||||
#define __NR_reboot (__X32_SYSCALL_BIT + 169)
|
||||
#define __NR_sethostname (__X32_SYSCALL_BIT + 170)
|
||||
#define __NR_setdomainname (__X32_SYSCALL_BIT + 171)
|
||||
#define __NR_iopl (__X32_SYSCALL_BIT + 172)
|
||||
#define __NR_ioperm (__X32_SYSCALL_BIT + 173)
|
||||
#define __NR_init_module (__X32_SYSCALL_BIT + 175)
|
||||
#define __NR_delete_module (__X32_SYSCALL_BIT + 176)
|
||||
#define __NR_quotactl (__X32_SYSCALL_BIT + 179)
|
||||
#define __NR_getpmsg (__X32_SYSCALL_BIT + 181)
|
||||
#define __NR_putpmsg (__X32_SYSCALL_BIT + 182)
|
||||
#define __NR_afs_syscall (__X32_SYSCALL_BIT + 183)
|
||||
#define __NR_tuxcall (__X32_SYSCALL_BIT + 184)
|
||||
#define __NR_security (__X32_SYSCALL_BIT + 185)
|
||||
#define __NR_gettid (__X32_SYSCALL_BIT + 186)
|
||||
#define __NR_readahead (__X32_SYSCALL_BIT + 187)
|
||||
#define __NR_setxattr (__X32_SYSCALL_BIT + 188)
|
||||
#define __NR_lsetxattr (__X32_SYSCALL_BIT + 189)
|
||||
#define __NR_fsetxattr (__X32_SYSCALL_BIT + 190)
|
||||
#define __NR_getxattr (__X32_SYSCALL_BIT + 191)
|
||||
#define __NR_lgetxattr (__X32_SYSCALL_BIT + 192)
|
||||
#define __NR_fgetxattr (__X32_SYSCALL_BIT + 193)
|
||||
#define __NR_listxattr (__X32_SYSCALL_BIT + 194)
|
||||
#define __NR_llistxattr (__X32_SYSCALL_BIT + 195)
|
||||
#define __NR_flistxattr (__X32_SYSCALL_BIT + 196)
|
||||
#define __NR_removexattr (__X32_SYSCALL_BIT + 197)
|
||||
#define __NR_lremovexattr (__X32_SYSCALL_BIT + 198)
|
||||
#define __NR_fremovexattr (__X32_SYSCALL_BIT + 199)
|
||||
#define __NR_tkill (__X32_SYSCALL_BIT + 200)
|
||||
#define __NR_time (__X32_SYSCALL_BIT + 201)
|
||||
#define __NR_futex (__X32_SYSCALL_BIT + 202)
|
||||
#define __NR_sched_setaffinity (__X32_SYSCALL_BIT + 203)
|
||||
#define __NR_sched_getaffinity (__X32_SYSCALL_BIT + 204)
|
||||
#define __NR_io_destroy (__X32_SYSCALL_BIT + 207)
|
||||
#define __NR_io_getevents (__X32_SYSCALL_BIT + 208)
|
||||
#define __NR_io_cancel (__X32_SYSCALL_BIT + 210)
|
||||
#define __NR_lookup_dcookie (__X32_SYSCALL_BIT + 212)
|
||||
#define __NR_epoll_create (__X32_SYSCALL_BIT + 213)
|
||||
#define __NR_remap_file_pages (__X32_SYSCALL_BIT + 216)
|
||||
#define __NR_getdents64 (__X32_SYSCALL_BIT + 217)
|
||||
#define __NR_set_tid_address (__X32_SYSCALL_BIT + 218)
|
||||
#define __NR_restart_syscall (__X32_SYSCALL_BIT + 219)
|
||||
#define __NR_semtimedop (__X32_SYSCALL_BIT + 220)
|
||||
#define __NR_fadvise64 (__X32_SYSCALL_BIT + 221)
|
||||
#define __NR_timer_settime (__X32_SYSCALL_BIT + 223)
|
||||
#define __NR_timer_gettime (__X32_SYSCALL_BIT + 224)
|
||||
#define __NR_timer_getoverrun (__X32_SYSCALL_BIT + 225)
|
||||
#define __NR_timer_delete (__X32_SYSCALL_BIT + 226)
|
||||
#define __NR_clock_settime (__X32_SYSCALL_BIT + 227)
|
||||
#define __NR_clock_gettime (__X32_SYSCALL_BIT + 228)
|
||||
#define __NR_clock_getres (__X32_SYSCALL_BIT + 229)
|
||||
#define __NR_clock_nanosleep (__X32_SYSCALL_BIT + 230)
|
||||
#define __NR_exit_group (__X32_SYSCALL_BIT + 231)
|
||||
#define __NR_epoll_wait (__X32_SYSCALL_BIT + 232)
|
||||
#define __NR_epoll_ctl (__X32_SYSCALL_BIT + 233)
|
||||
#define __NR_tgkill (__X32_SYSCALL_BIT + 234)
|
||||
#define __NR_utimes (__X32_SYSCALL_BIT + 235)
|
||||
#define __NR_mbind (__X32_SYSCALL_BIT + 237)
|
||||
#define __NR_set_mempolicy (__X32_SYSCALL_BIT + 238)
|
||||
#define __NR_get_mempolicy (__X32_SYSCALL_BIT + 239)
|
||||
#define __NR_mq_open (__X32_SYSCALL_BIT + 240)
|
||||
#define __NR_mq_unlink (__X32_SYSCALL_BIT + 241)
|
||||
#define __NR_mq_timedsend (__X32_SYSCALL_BIT + 242)
|
||||
#define __NR_mq_timedreceive (__X32_SYSCALL_BIT + 243)
|
||||
#define __NR_mq_getsetattr (__X32_SYSCALL_BIT + 245)
|
||||
#define __NR_add_key (__X32_SYSCALL_BIT + 248)
|
||||
#define __NR_request_key (__X32_SYSCALL_BIT + 249)
|
||||
#define __NR_keyctl (__X32_SYSCALL_BIT + 250)
|
||||
#define __NR_ioprio_set (__X32_SYSCALL_BIT + 251)
|
||||
#define __NR_ioprio_get (__X32_SYSCALL_BIT + 252)
|
||||
#define __NR_inotify_init (__X32_SYSCALL_BIT + 253)
|
||||
#define __NR_inotify_add_watch (__X32_SYSCALL_BIT + 254)
|
||||
#define __NR_inotify_rm_watch (__X32_SYSCALL_BIT + 255)
|
||||
#define __NR_migrate_pages (__X32_SYSCALL_BIT + 256)
|
||||
#define __NR_openat (__X32_SYSCALL_BIT + 257)
|
||||
#define __NR_mkdirat (__X32_SYSCALL_BIT + 258)
|
||||
#define __NR_mknodat (__X32_SYSCALL_BIT + 259)
|
||||
#define __NR_fchownat (__X32_SYSCALL_BIT + 260)
|
||||
#define __NR_futimesat (__X32_SYSCALL_BIT + 261)
|
||||
#define __NR_newfstatat (__X32_SYSCALL_BIT + 262)
|
||||
#define __NR_unlinkat (__X32_SYSCALL_BIT + 263)
|
||||
#define __NR_renameat (__X32_SYSCALL_BIT + 264)
|
||||
#define __NR_linkat (__X32_SYSCALL_BIT + 265)
|
||||
#define __NR_symlinkat (__X32_SYSCALL_BIT + 266)
|
||||
#define __NR_readlinkat (__X32_SYSCALL_BIT + 267)
|
||||
#define __NR_fchmodat (__X32_SYSCALL_BIT + 268)
|
||||
#define __NR_faccessat (__X32_SYSCALL_BIT + 269)
|
||||
#define __NR_pselect6 (__X32_SYSCALL_BIT + 270)
|
||||
#define __NR_ppoll (__X32_SYSCALL_BIT + 271)
|
||||
#define __NR_unshare (__X32_SYSCALL_BIT + 272)
|
||||
#define __NR_splice (__X32_SYSCALL_BIT + 275)
|
||||
#define __NR_tee (__X32_SYSCALL_BIT + 276)
|
||||
#define __NR_sync_file_range (__X32_SYSCALL_BIT + 277)
|
||||
#define __NR_utimensat (__X32_SYSCALL_BIT + 280)
|
||||
#define __NR_epoll_pwait (__X32_SYSCALL_BIT + 281)
|
||||
#define __NR_signalfd (__X32_SYSCALL_BIT + 282)
|
||||
#define __NR_timerfd_create (__X32_SYSCALL_BIT + 283)
|
||||
#define __NR_eventfd (__X32_SYSCALL_BIT + 284)
|
||||
#define __NR_fallocate (__X32_SYSCALL_BIT + 285)
|
||||
#define __NR_timerfd_settime (__X32_SYSCALL_BIT + 286)
|
||||
#define __NR_timerfd_gettime (__X32_SYSCALL_BIT + 287)
|
||||
#define __NR_accept4 (__X32_SYSCALL_BIT + 288)
|
||||
#define __NR_signalfd4 (__X32_SYSCALL_BIT + 289)
|
||||
#define __NR_eventfd2 (__X32_SYSCALL_BIT + 290)
|
||||
#define __NR_epoll_create1 (__X32_SYSCALL_BIT + 291)
|
||||
#define __NR_dup3 (__X32_SYSCALL_BIT + 292)
|
||||
#define __NR_pipe2 (__X32_SYSCALL_BIT + 293)
|
||||
#define __NR_inotify_init1 (__X32_SYSCALL_BIT + 294)
|
||||
#define __NR_perf_event_open (__X32_SYSCALL_BIT + 298)
|
||||
#define __NR_fanotify_init (__X32_SYSCALL_BIT + 300)
|
||||
#define __NR_fanotify_mark (__X32_SYSCALL_BIT + 301)
|
||||
#define __NR_prlimit64 (__X32_SYSCALL_BIT + 302)
|
||||
#define __NR_name_to_handle_at (__X32_SYSCALL_BIT + 303)
|
||||
#define __NR_open_by_handle_at (__X32_SYSCALL_BIT + 304)
|
||||
#define __NR_clock_adjtime (__X32_SYSCALL_BIT + 305)
|
||||
#define __NR_syncfs (__X32_SYSCALL_BIT + 306)
|
||||
#define __NR_setns (__X32_SYSCALL_BIT + 308)
|
||||
#define __NR_getcpu (__X32_SYSCALL_BIT + 309)
|
||||
#define __NR_kcmp (__X32_SYSCALL_BIT + 312)
|
||||
#define __NR_finit_module (__X32_SYSCALL_BIT + 313)
|
||||
#define __NR_sched_setattr (__X32_SYSCALL_BIT + 314)
|
||||
#define __NR_sched_getattr (__X32_SYSCALL_BIT + 315)
|
||||
#define __NR_renameat2 (__X32_SYSCALL_BIT + 316)
|
||||
#define __NR_seccomp (__X32_SYSCALL_BIT + 317)
|
||||
#define __NR_getrandom (__X32_SYSCALL_BIT + 318)
|
||||
#define __NR_memfd_create (__X32_SYSCALL_BIT + 319)
|
||||
#define __NR_kexec_file_load (__X32_SYSCALL_BIT + 320)
|
||||
#define __NR_bpf (__X32_SYSCALL_BIT + 321)
|
||||
#define __NR_userfaultfd (__X32_SYSCALL_BIT + 323)
|
||||
#define __NR_membarrier (__X32_SYSCALL_BIT + 324)
|
||||
#define __NR_mlock2 (__X32_SYSCALL_BIT + 325)
|
||||
#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
|
||||
#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
|
||||
#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
|
||||
#define __NR_readv (__X32_SYSCALL_BIT + 515)
|
||||
#define __NR_writev (__X32_SYSCALL_BIT + 516)
|
||||
#define __NR_recvfrom (__X32_SYSCALL_BIT + 517)
|
||||
#define __NR_sendmsg (__X32_SYSCALL_BIT + 518)
|
||||
#define __NR_recvmsg (__X32_SYSCALL_BIT + 519)
|
||||
#define __NR_execve (__X32_SYSCALL_BIT + 520)
|
||||
#define __NR_ptrace (__X32_SYSCALL_BIT + 521)
|
||||
#define __NR_rt_sigpending (__X32_SYSCALL_BIT + 522)
|
||||
#define __NR_rt_sigtimedwait (__X32_SYSCALL_BIT + 523)
|
||||
#define __NR_rt_sigqueueinfo (__X32_SYSCALL_BIT + 524)
|
||||
#define __NR_sigaltstack (__X32_SYSCALL_BIT + 525)
|
||||
#define __NR_timer_create (__X32_SYSCALL_BIT + 526)
|
||||
#define __NR_mq_notify (__X32_SYSCALL_BIT + 527)
|
||||
#define __NR_kexec_load (__X32_SYSCALL_BIT + 528)
|
||||
#define __NR_waitid (__X32_SYSCALL_BIT + 529)
|
||||
#define __NR_set_robust_list (__X32_SYSCALL_BIT + 530)
|
||||
#define __NR_get_robust_list (__X32_SYSCALL_BIT + 531)
|
||||
#define __NR_vmsplice (__X32_SYSCALL_BIT + 532)
|
||||
#define __NR_move_pages (__X32_SYSCALL_BIT + 533)
|
||||
#define __NR_preadv (__X32_SYSCALL_BIT + 534)
|
||||
#define __NR_pwritev (__X32_SYSCALL_BIT + 535)
|
||||
#define __NR_rt_tgsigqueueinfo (__X32_SYSCALL_BIT + 536)
|
||||
#define __NR_recvmmsg (__X32_SYSCALL_BIT + 537)
|
||||
#define __NR_sendmmsg (__X32_SYSCALL_BIT + 538)
|
||||
#define __NR_process_vm_readv (__X32_SYSCALL_BIT + 539)
|
||||
#define __NR_process_vm_writev (__X32_SYSCALL_BIT + 540)
|
||||
#define __NR_setsockopt (__X32_SYSCALL_BIT + 541)
|
||||
#define __NR_getsockopt (__X32_SYSCALL_BIT + 542)
|
||||
#define __NR_io_setup (__X32_SYSCALL_BIT + 543)
|
||||
#define __NR_io_submit (__X32_SYSCALL_BIT + 544)
|
||||
#define __NR_execveat (__X32_SYSCALL_BIT + 545)
|
||||
|
||||
#endif /* _ASM_X86_UNISTD_X32_H */
|
||||
@ -0,0 +1,129 @@
|
||||
#ifndef _ASM_X86_VM86_H
|
||||
#define _ASM_X86_VM86_H
|
||||
|
||||
/*
|
||||
* I'm guessing at the VIF/VIP flag usage, but hope that this is how
|
||||
* the Pentium uses them. Linux will return from vm86 mode when both
|
||||
* VIF and VIP is set.
|
||||
*
|
||||
* On a Pentium, we could probably optimize the virtual flags directly
|
||||
* in the eflags register instead of doing it "by hand" in vflags...
|
||||
*
|
||||
* Linus
|
||||
*/
|
||||
|
||||
#include <asm/processor-flags.h>
|
||||
|
||||
#define BIOSSEG 0x0f000
|
||||
|
||||
#define CPU_086 0
|
||||
#define CPU_186 1
|
||||
#define CPU_286 2
|
||||
#define CPU_386 3
|
||||
#define CPU_486 4
|
||||
#define CPU_586 5
|
||||
|
||||
/*
|
||||
* Return values for the 'vm86()' system call
|
||||
*/
|
||||
#define VM86_TYPE(retval) ((retval) & 0xff)
|
||||
#define VM86_ARG(retval) ((retval) >> 8)
|
||||
|
||||
#define VM86_SIGNAL 0 /* return due to signal */
|
||||
#define VM86_UNKNOWN 1 /* unhandled GP fault
|
||||
- IO-instruction or similar */
|
||||
#define VM86_INTx 2 /* int3/int x instruction (ARG = x) */
|
||||
#define VM86_STI 3 /* sti/popf/iret instruction enabled
|
||||
virtual interrupts */
|
||||
|
||||
/*
|
||||
* Additional return values when invoking new vm86()
|
||||
*/
|
||||
#define VM86_PICRETURN 4 /* return due to pending PIC request */
|
||||
#define VM86_TRAP 6 /* return due to DOS-debugger request */
|
||||
|
||||
/*
|
||||
* function codes when invoking new vm86()
|
||||
*/
|
||||
#define VM86_PLUS_INSTALL_CHECK 0
|
||||
#define VM86_ENTER 1
|
||||
#define VM86_ENTER_NO_BYPASS 2
|
||||
#define VM86_REQUEST_IRQ 3
|
||||
#define VM86_FREE_IRQ 4
|
||||
#define VM86_GET_IRQ_BITS 5
|
||||
#define VM86_GET_AND_RESET_IRQ 6
|
||||
|
||||
/*
|
||||
* This is the stack-layout seen by the user space program when we have
|
||||
* done a translation of "SAVE_ALL" from vm86 mode. The real kernel layout
|
||||
* is 'kernel_vm86_regs' (see below).
|
||||
*/
|
||||
|
||||
struct vm86_regs {
|
||||
/*
|
||||
* normal regs, with special meaning for the segment descriptors..
|
||||
*/
|
||||
long ebx;
|
||||
long ecx;
|
||||
long edx;
|
||||
long esi;
|
||||
long edi;
|
||||
long ebp;
|
||||
long eax;
|
||||
long __null_ds;
|
||||
long __null_es;
|
||||
long __null_fs;
|
||||
long __null_gs;
|
||||
long orig_eax;
|
||||
long eip;
|
||||
unsigned short cs, __csh;
|
||||
long eflags;
|
||||
long esp;
|
||||
unsigned short ss, __ssh;
|
||||
/*
|
||||
* these are specific to v86 mode:
|
||||
*/
|
||||
unsigned short es, __esh;
|
||||
unsigned short ds, __dsh;
|
||||
unsigned short fs, __fsh;
|
||||
unsigned short gs, __gsh;
|
||||
};
|
||||
|
||||
struct revectored_struct {
|
||||
unsigned long __map[8]; /* 256 bits */
|
||||
};
|
||||
|
||||
struct vm86_struct {
|
||||
struct vm86_regs regs;
|
||||
unsigned long flags;
|
||||
unsigned long screen_bitmap;
|
||||
unsigned long cpu_type;
|
||||
struct revectored_struct int_revectored;
|
||||
struct revectored_struct int21_revectored;
|
||||
};
|
||||
|
||||
/*
|
||||
* flags masks
|
||||
*/
|
||||
#define VM86_SCREEN_BITMAP 0x0001
|
||||
|
||||
struct vm86plus_info_struct {
|
||||
unsigned long force_return_for_pic:1;
|
||||
unsigned long vm86dbg_active:1; /* for debugger */
|
||||
unsigned long vm86dbg_TFpendig:1; /* for debugger */
|
||||
unsigned long unused:28;
|
||||
unsigned long is_vm86pus:1; /* for vm86 internal use */
|
||||
unsigned char vm86dbg_intxxtab[32]; /* for debugger */
|
||||
};
|
||||
struct vm86plus_struct {
|
||||
struct vm86_regs regs;
|
||||
unsigned long flags;
|
||||
unsigned long screen_bitmap;
|
||||
unsigned long cpu_type;
|
||||
struct revectored_struct int_revectored;
|
||||
struct revectored_struct int21_revectored;
|
||||
struct vm86plus_info_struct vm86plus;
|
||||
};
|
||||
|
||||
|
||||
#endif /* _ASM_X86_VM86_H */
|
||||
@ -0,0 +1,136 @@
|
||||
/*
|
||||
* vmx.h: VMX Architecture related definitions
|
||||
* Copyright (c) 2004, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
* A few random additions are:
|
||||
* Copyright (C) 2006 Qumranet
|
||||
* Avi Kivity <avi@qumranet.com>
|
||||
* Yaniv Kamay <yaniv@qumranet.com>
|
||||
*
|
||||
*/
|
||||
#ifndef VMX_H
|
||||
#define VMX_H
|
||||
|
||||
|
||||
#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
|
||||
|
||||
#define EXIT_REASON_EXCEPTION_NMI 0
|
||||
#define EXIT_REASON_EXTERNAL_INTERRUPT 1
|
||||
#define EXIT_REASON_TRIPLE_FAULT 2
|
||||
|
||||
#define EXIT_REASON_PENDING_INTERRUPT 7
|
||||
#define EXIT_REASON_NMI_WINDOW 8
|
||||
#define EXIT_REASON_TASK_SWITCH 9
|
||||
#define EXIT_REASON_CPUID 10
|
||||
#define EXIT_REASON_HLT 12
|
||||
#define EXIT_REASON_INVD 13
|
||||
#define EXIT_REASON_INVLPG 14
|
||||
#define EXIT_REASON_RDPMC 15
|
||||
#define EXIT_REASON_RDTSC 16
|
||||
#define EXIT_REASON_VMCALL 18
|
||||
#define EXIT_REASON_VMCLEAR 19
|
||||
#define EXIT_REASON_VMLAUNCH 20
|
||||
#define EXIT_REASON_VMPTRLD 21
|
||||
#define EXIT_REASON_VMPTRST 22
|
||||
#define EXIT_REASON_VMREAD 23
|
||||
#define EXIT_REASON_VMRESUME 24
|
||||
#define EXIT_REASON_VMWRITE 25
|
||||
#define EXIT_REASON_VMOFF 26
|
||||
#define EXIT_REASON_VMON 27
|
||||
#define EXIT_REASON_CR_ACCESS 28
|
||||
#define EXIT_REASON_DR_ACCESS 29
|
||||
#define EXIT_REASON_IO_INSTRUCTION 30
|
||||
#define EXIT_REASON_MSR_READ 31
|
||||
#define EXIT_REASON_MSR_WRITE 32
|
||||
#define EXIT_REASON_INVALID_STATE 33
|
||||
#define EXIT_REASON_MSR_LOAD_FAIL 34
|
||||
#define EXIT_REASON_MWAIT_INSTRUCTION 36
|
||||
#define EXIT_REASON_MONITOR_TRAP_FLAG 37
|
||||
#define EXIT_REASON_MONITOR_INSTRUCTION 39
|
||||
#define EXIT_REASON_PAUSE_INSTRUCTION 40
|
||||
#define EXIT_REASON_MCE_DURING_VMENTRY 41
|
||||
#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
|
||||
#define EXIT_REASON_APIC_ACCESS 44
|
||||
#define EXIT_REASON_EOI_INDUCED 45
|
||||
#define EXIT_REASON_EPT_VIOLATION 48
|
||||
#define EXIT_REASON_EPT_MISCONFIG 49
|
||||
#define EXIT_REASON_INVEPT 50
|
||||
#define EXIT_REASON_RDTSCP 51
|
||||
#define EXIT_REASON_PREEMPTION_TIMER 52
|
||||
#define EXIT_REASON_INVVPID 53
|
||||
#define EXIT_REASON_WBINVD 54
|
||||
#define EXIT_REASON_XSETBV 55
|
||||
#define EXIT_REASON_APIC_WRITE 56
|
||||
#define EXIT_REASON_INVPCID 58
|
||||
#define EXIT_REASON_PML_FULL 62
|
||||
#define EXIT_REASON_XSAVES 63
|
||||
#define EXIT_REASON_XRSTORS 64
|
||||
#define EXIT_REASON_PCOMMIT 65
|
||||
|
||||
#define VMX_EXIT_REASONS \
|
||||
{ EXIT_REASON_EXCEPTION_NMI, "EXCEPTION_NMI" }, \
|
||||
{ EXIT_REASON_EXTERNAL_INTERRUPT, "EXTERNAL_INTERRUPT" }, \
|
||||
{ EXIT_REASON_TRIPLE_FAULT, "TRIPLE_FAULT" }, \
|
||||
{ EXIT_REASON_PENDING_INTERRUPT, "PENDING_INTERRUPT" }, \
|
||||
{ EXIT_REASON_NMI_WINDOW, "NMI_WINDOW" }, \
|
||||
{ EXIT_REASON_TASK_SWITCH, "TASK_SWITCH" }, \
|
||||
{ EXIT_REASON_CPUID, "CPUID" }, \
|
||||
{ EXIT_REASON_HLT, "HLT" }, \
|
||||
{ EXIT_REASON_INVLPG, "INVLPG" }, \
|
||||
{ EXIT_REASON_RDPMC, "RDPMC" }, \
|
||||
{ EXIT_REASON_RDTSC, "RDTSC" }, \
|
||||
{ EXIT_REASON_VMCALL, "VMCALL" }, \
|
||||
{ EXIT_REASON_VMCLEAR, "VMCLEAR" }, \
|
||||
{ EXIT_REASON_VMLAUNCH, "VMLAUNCH" }, \
|
||||
{ EXIT_REASON_VMPTRLD, "VMPTRLD" }, \
|
||||
{ EXIT_REASON_VMPTRST, "VMPTRST" }, \
|
||||
{ EXIT_REASON_VMREAD, "VMREAD" }, \
|
||||
{ EXIT_REASON_VMRESUME, "VMRESUME" }, \
|
||||
{ EXIT_REASON_VMWRITE, "VMWRITE" }, \
|
||||
{ EXIT_REASON_VMOFF, "VMOFF" }, \
|
||||
{ EXIT_REASON_VMON, "VMON" }, \
|
||||
{ EXIT_REASON_CR_ACCESS, "CR_ACCESS" }, \
|
||||
{ EXIT_REASON_DR_ACCESS, "DR_ACCESS" }, \
|
||||
{ EXIT_REASON_IO_INSTRUCTION, "IO_INSTRUCTION" }, \
|
||||
{ EXIT_REASON_MSR_READ, "MSR_READ" }, \
|
||||
{ EXIT_REASON_MSR_WRITE, "MSR_WRITE" }, \
|
||||
{ EXIT_REASON_MWAIT_INSTRUCTION, "MWAIT_INSTRUCTION" }, \
|
||||
{ EXIT_REASON_MONITOR_TRAP_FLAG, "MONITOR_TRAP_FLAG" }, \
|
||||
{ EXIT_REASON_MONITOR_INSTRUCTION, "MONITOR_INSTRUCTION" }, \
|
||||
{ EXIT_REASON_PAUSE_INSTRUCTION, "PAUSE_INSTRUCTION" }, \
|
||||
{ EXIT_REASON_MCE_DURING_VMENTRY, "MCE_DURING_VMENTRY" }, \
|
||||
{ EXIT_REASON_TPR_BELOW_THRESHOLD, "TPR_BELOW_THRESHOLD" }, \
|
||||
{ EXIT_REASON_APIC_ACCESS, "APIC_ACCESS" }, \
|
||||
{ EXIT_REASON_EPT_VIOLATION, "EPT_VIOLATION" }, \
|
||||
{ EXIT_REASON_EPT_MISCONFIG, "EPT_MISCONFIG" }, \
|
||||
{ EXIT_REASON_INVEPT, "INVEPT" }, \
|
||||
{ EXIT_REASON_PREEMPTION_TIMER, "PREEMPTION_TIMER" }, \
|
||||
{ EXIT_REASON_WBINVD, "WBINVD" }, \
|
||||
{ EXIT_REASON_APIC_WRITE, "APIC_WRITE" }, \
|
||||
{ EXIT_REASON_EOI_INDUCED, "EOI_INDUCED" }, \
|
||||
{ EXIT_REASON_INVALID_STATE, "INVALID_STATE" }, \
|
||||
{ EXIT_REASON_MSR_LOAD_FAIL, "MSR_LOAD_FAIL" }, \
|
||||
{ EXIT_REASON_INVD, "INVD" }, \
|
||||
{ EXIT_REASON_INVVPID, "INVVPID" }, \
|
||||
{ EXIT_REASON_INVPCID, "INVPCID" }, \
|
||||
{ EXIT_REASON_XSAVES, "XSAVES" }, \
|
||||
{ EXIT_REASON_XRSTORS, "XRSTORS" }, \
|
||||
{ EXIT_REASON_PCOMMIT, "PCOMMIT" }
|
||||
|
||||
#define VMX_ABORT_SAVE_GUEST_MSR_FAIL 1
|
||||
#define VMX_ABORT_LOAD_HOST_MSR_FAIL 4
|
||||
|
||||
#endif /* VMX_H */
|
||||
@ -0,0 +1,12 @@
|
||||
#ifndef _ASM_X86_VSYSCALL_H
|
||||
#define _ASM_X86_VSYSCALL_H
|
||||
|
||||
enum vsyscall_num {
|
||||
__NR_vgettimeofday,
|
||||
__NR_vtime,
|
||||
__NR_vgetcpu,
|
||||
};
|
||||
|
||||
#define VSYSCALL_ADDR (-10UL << 20)
|
||||
|
||||
#endif /* _ASM_X86_VSYSCALL_H */
|
||||
Reference in New Issue
Block a user